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| litghost | daveshah: I haven't seen any activity on https://github.com/YosysHQ/yosys/pull/928 , is it in an acceptable form? | 00:02 |
|---|---|---|
| tpb | Title: Add additional cells sim models for core 7-series primitives. by litghost · Pull Request #928 · YosysHQ/yosys · GitHub (at github.com) | 00:02 |
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| mithro | Why do some of the D flip flop models start with $_DFF and some start with $__DFF ? | 02:26 |
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| daveshah | litghost: I've just asked Eddie to review | 08:26 |
| daveshah | mithro: the $_ cells are "first class" gate-level cells that are supported throughout Yosys (eg for abc, opt, etc) whereas $__ cells are special-purpose cells | 08:27 |
| daveshah | The $__ cells are generally only supported between one or a couple of passes and intended to be short-lived intermediate cells | 08:28 |
| daveshah | The intention being you would then techmap them to arch-specific cells | 08:28 |
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| litghost | daveshah: Thanks! I have trouble knowing who should be notified to take a look at reviews | 15:09 |
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| mithro | daveshah: Is this a liberty file? -> https://github.com/YosysHQ/yosys/blob/master/techlibs/common/cells.lib ? | 20:44 |
| tpb | Title: yosys/cells.lib at master · YosysHQ/yosys · GitHub (at github.com) | 20:44 |
| daveshah | mithro: yes | 20:45 |
| mithro | daveshah: Do you have a reference on how a liberty file works? I'm trying to understand what the function: "IQ" and ff(IQ, IQN) {} bits work? | 20:47 |
| daveshah | mithro: maybe have a look at https://people.eecs.berkeley.edu/~alanmi/publications/other/liberty07_03.pdf | 20:48 |
| mithro | daveshah: Had that doc already open -- it only has one reference to "function:"... -- the ff Group section seems to have some of what I'm after but it is not the clearest.... Most of the docs I have so far are more interested in things like temp, voltage, process, etc... | 20:59 |
| mithro | daveshah: Looks like https://media.c3d2.de/mgoblin_media/media_entries/659/Liberty_User_Guides_and_Reference_Manual_Suite_Version_2017.06.pdf might be a good reference... | 21:02 |
| daveshah | ff(IQ, IQN) defines a flipflop with non-inverting output variable IQ and inverting output variable IQN | 21:02 |
| daveshah | next_state specifies that the state after a clock edge is D | 21:03 |
| daveshah | function gives the logic function for a pin | 21:03 |
| daveshah | function: "IQ" means the pin simply mirrors the IQ variable (ie the FF state) | 21:03 |
| daveshah | also FYI, you can combine read_liberty and write_verilog to convert liberty to verilog with Yosys | 21:04 |
| mithro | daveshah: Is there a write_liberty? | 21:05 |
| daveshah | No | 21:05 |
| daveshah | It's not something anyone has had a use case before | 21:06 |
| daveshah | A simple implementation probably wouldn't be too hard | 21:06 |
| mithro | daveshah: Does adff means async dff? -> https://github.com/YosysHQ/yosys/blob/master/techlibs/common/adff2dff.v | 21:09 |
| tpb | Title: yosys/adff2dff.v at master · YosysHQ/yosys · GitHub (at github.com) | 21:09 |
| daveshah | Yes | 21:10 |
| mithro | daveshah: So that is an Async DFF to Sync DFF techmap? | 21:10 |
| daveshah | Yes | 21:12 |
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| mithro | daveshah: eddie mentioned that ASIC designers mainly use liberty files for timing - does yosys already read timing information from liberty files at all? | 21:32 |
| daveshah | mithro: No, but abc does (when used with Yosys it takes a liberty file directly rather than going through read_liberty) | 21:35 |
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| mithro | daveshah: looking at module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule | 22:22 |
| mithro | daveshah: Doesn't that have 1 to many values in the flip flop name? | 22:22 |
| daveshah | No | 22:23 |
| mithro | What are the 3 values for? | 22:23 |
| daveshah | Negative clock, negative set/reset, reset | 22:23 |
| mithro | daveshah: The reset == value when negative set/reset occurs? | 22:24 |
| daveshah | Yes | 22:25 |
| daveshah | $__DFFS is a special synchronous set/reset DFF used by dff2dffs and the ECP5 techmap rules only | 22:26 |
| daveshah | (S=synchronous) | 22:26 |
| FL4SHK | so, I'm looking at the yosys GitHub README | 22:26 |
| FL4SHK | the supported features of SystemVerilog lists interfaces... and modports | 22:27 |
| FL4SHK | but it doesn't seem to synthesize the use of those features as module ports? | 22:27 |
| FL4SHK | (yes, I know I've talked about this multiple days in a row now) | 22:27 |
| mithro | daveshah: and $__DFFE_NN0 is the async set/reset version? | 22:28 |
| daveshah | Yes, also with enable | 22:28 |
| daveshah | FL4SHK: have you looked at the interface tests? Eg https://github.com/YosysHQ/yosys/blob/master/tests/svinterfaces/svinterface1.sv | 22:29 |
| tpb | Title: yosys/svinterface1.sv at master · YosysHQ/yosys · GitHub (at github.com) | 22:29 |
| daveshah | I don't know much about SV interfaces, so can't help much more than that | 22:29 |
| mithro | daveshah: $__DFFE_NN0- Clock Negative, Enable Negative, Set/Reset - ???, Value on Reset 0 ?? | 22:30 |
| daveshah | Negative clock, negative set/reset, positive enable | 22:31 |
| mithro | daveshah: the ECP only has positive enables? | 22:31 |
| FL4SHK | wait | 22:31 |
| FL4SHK | daveshah: wait | 22:31 |
| FL4SHK | maybe I did something wrongly! | 22:31 |
| FL4SHK | now I've got to give it a try again | 22:31 |
| daveshah | mithro: No, but Yosys only supports positive enables iirc | 22:31 |
| mithro | $_DFFE_PN_ (D, C, E, Q) - A positive edge D-type flip-flop with negative polarity enable. ? | 22:32 |
| daveshah | Ah, looks like it only supports them without set/reset | 22:33 |
| FL4SHK | daveshah: you may have made my day | 22:33 |
| FL4SHK | thank you :P | 22:33 |
| FL4SHK | that example is EXACTLY what I was looking for | 22:33 |
| FL4SHK | ...how can I contribute more? | 22:33 |
| FL4SHK | er, how can I contribute to yosys? | 22:33 |
| daveshah | FL4SHK: is there anything in particular you want to work on? | 22:34 |
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| FL4SHK | typedef, struct, enum | 22:34 |
| daveshah | All of those would be great contributions | 22:34 |
| FL4SHK | I've been working on my own compiler thing | 22:34 |
| mithro | daveshah: I'm trying to build a table of flip flops at https://docs.google.com/spreadsheets/d/16yvScRkedOkPCRBSInFuHE_cUMD8Ls-b9KFmHocpC-o/edit#gid=0 | 22:35 |
| tpb | Title: Flip Flops - Google Sheets (at docs.google.com) | 22:35 |
| FL4SHK | but contributing to yosys may actually be a better idea | 22:35 |
| daveshah | mithro: DFFS/DFFSE are sync | 22:36 |
| daveshah | DFFSR have both an async set and reset (and consequently don't map to most FPGA arches) | 22:36 |
| FL4SHK | ...I do wish you could parameterize structs, btw | 22:36 |
| FL4SHK | oh, yeah | 22:37 |
| FL4SHK | one other thing: `type` | 22:37 |
| FL4SHK | that's one thing that would be... useful | 22:37 |
| mithro | daveshah: So, $_DFFSR_ should be async? | 22:37 |
| daveshah | mithro: yes | 22:37 |
| daveshah | https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v | 22:38 |
| tpb | Title: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com) | 22:38 |
| mithro | daveshah: Is it when there is a 0 or 1 in the truth table that it is async? | 22:39 |
| daveshah | Or just look at the sensitivity list | 22:39 |
| mithro | daveshah: It is async if both the clock and reset signal is in the sensitivity list? | 22:41 |
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| daveshah | Yes | 22:41 |
| FL4SHK | Is the open source form of yosys used for commercial applications, or do companies generally want to use the commercial version? | 22:54 |
| daveshah | Depends what people are doing | 22:55 |
| mithro | FL4SHK: Also depends on how you defined "commercial applications" | 22:55 |
| daveshah | I know quite a few commercial users of open source Yosys (eg because they want a fully open flow) | 22:55 |
| daveshah | Others need full VHDL and SV | 22:55 |
| FL4SHK | I do FPGA dev professionally... and I'm concerned about there being a conflict of interest | 22:56 |
| FL4SHK | ...don't want to lose my job | 22:56 |
| daveshah | Probably fine if you don't work for a company that writes HDL frontends | 22:57 |
| FL4SHK | I don't | 22:57 |
| daveshah | But do check your T&Cs | 22:57 |
| FL4SHK | I think I'm safe to *use* yosys, at least | 22:57 |
| daveshah | The one thing to avoid is benchmarking - particularly publicly - against anything commercial you have at work | 22:58 |
| daveshah | That's almost always banned in the EULA | 22:58 |
| FL4SHK | I don't think I can even install yosys at work | 22:59 |
| mithro | FL4SHK: You would have to ask your companies legal council - generally though the software is under a *very* permissive license | 22:59 |
| daveshah | Yes, we don't require copyright assignment or anything like that | 22:59 |
| FL4SHK | could we consider the version of SystemVerilog that the open source version of yosys implements to be a "custom language" on account of it not being anywhere near complete? | 23:00 |
| FL4SHK | because... I may be safe, then | 23:00 |
| mithro | FL4SHK: Google has released their "best practice for compliance with open source licenses" you can read if your interested -> https://opensource.google.com/docs/thirdparty/licenses/#notice | 23:00 |
| tpb | Title: Licenses – opensource.google.com (at opensource.google.com) | 23:00 |
| FL4SHK | mithro: it's actually not the open source licenses I'm concerned about | 23:01 |
| daveshah | FL4SHK: well, Yosys does have a few non-standard extensions mostly for formal | 23:02 |
| FL4SHK | right | 23:02 |
| FL4SHK | or, at least for the Verilog side, anyway? | 23:02 |
| FL4SHK | with -sv, isn't the formal stuff a subset of what SystemVerilog has? | 23:02 |
| mithro | daveshah: _SR_ flip flops would be considered Async as they don't have any clocks, right? | 23:03 |
| daveshah | Yes, it also adds a few convenience things like $anyseq, $anyconst | 23:03 |
| FL4SHK | I think I'm at the very least safe to *use* yosys | 23:03 |
| FL4SHK | so even if I don't end up contributing... hmmm | 23:04 |
| daveshah | mithro: yes, although a latch might be a better description than a flipflop | 23:04 |
| FL4SHK | latches are normally banned outside of ASICs, eh? | 23:04 |
| daveshah | Yes | 23:04 |
| daveshah | Although there is some interesting research opportunity into doing fully async stuff with FPGAs | 23:05 |
| FL4SHK | ooh | 23:05 |
| FL4SHK | neat | 23:05 |
| FL4SHK | I didn't know that was happening. | 23:05 |
| daveshah | It's not something you want to do unless you know exactly what's going on | 23:05 |
| FL4SHK | Uh, right | 23:05 |
| daveshah | FPGAs aren't glitch free in general | 23:05 |
| FL4SHK | I've heard of async processors before. | 23:05 |
| mithro | daveshah: I actually talked to some people at Archonix yesterday | 23:05 |
| mithro | daveshah: They got out of the async FPGA game in the end :-( | 23:06 |
| daveshah | Ah, that's a shame | 23:06 |
| daveshah | I know a few people at my university are vaguely interested in async stuff | 23:06 |
| FL4SHK | I think I will hold off on attempting to contribute to yosys for now. | 23:07 |
| daveshah | eg http://async.org.uk/ay-festschrift/paper7-Alex-Festschrift.pdf | 23:07 |
| FL4SHK | but if someone else could... implement `typedef` and `enum`, I'd probably be really happy | 23:07 |
| FL4SHK | `struct`s are FAR less necessary when you have `interface`s. | 23:08 |
| FL4SHK | oh, here's a question I had: can yosys handle arrays on ports? | 23:08 |
| FL4SHK | for -sv | 23:08 |
| mithro | FL4SHK: There are quite a few people interested in support for those features... I think someone was even working on enums? | 23:08 |
| FL4SHK | oooh | 23:08 |
| FL4SHK | I can probably just wait for them to be implemented? | 23:09 |
| FL4SHK | ...I'm shocked that `interface`s are, by the way, but pleasantly so. | 23:09 |
| FL4SHK | I've been dying to be able to use `interface`s in formal | 23:09 |
| FL4SHK | and in design | 23:10 |
| FL4SHK | I was previously using Icarus Verilog to convert *its* subset of SystemVerilog into Verilog. That's how I originally did formal verification. | 23:10 |
| mithro | daveshah: You aren't making it to latchup right? | 23:12 |
| daveshah | No, exams :( | 23:12 |
| mithro | daveshah: You have exams with a masters program? Or hasn't that started yet? | 23:14 |
| daveshah | It's a integrated masters MEng | 23:14 |
| daveshah | So 4 years with no bachelors | 23:14 |
| mithro | daveshah: Ahh | 23:14 |
| FL4SHK | What are you doing your master's in/ | 23:15 |
| FL4SHK | ? | 23:15 |
| daveshah | Electronic and Information Engineering | 23:15 |
| FL4SHK | ah. I have a bachelor's in mechanical engineering, and a master's in electrical engineering. | 23:15 |
| FL4SHK | I just got the master's in December. | 23:15 |
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| mithro | What would you call "sync verse async" ? | 23:33 |
| ZipCPU | Async FF: always @(posedge i_clk, posedge i_reset) if (i_reset) Q <= 0; else Q <= D; | 23:35 |
| ZipCPU | Sync FF: always @(posedge i_clk) if (i_reset) Q <= 0; else Q <= D; | 23:36 |
| mithro | ZipCPU: I mean - like "Execution mode" or ? | 23:36 |
| ZipCPU | I must be missing something. What "execution mode" are you talking about? | 23:36 |
| mithro | ZipCPU: A flip flop can be sync or async right? What would you call this property of a flip flop? | 23:37 |
| ZipCPU | Yes, I would call that a property of the flip flop | 23:38 |
| mithro | ZipCPU: Yes but what is the name of this property of the flip flop? :-P | 23:38 |
| ZipCPU | Usually its the "synchronous or asynchronous reset" proeprty | 23:38 |
| ZipCPU | ... or some such | 23:38 |
| ZipCPU | Some FF's also have an asynchronous set property as well | 23:38 |
| FL4SHK | daveshah: so, out of curiosity, do interfaces instantiated in other interfaces work in yosys? | 23:48 |
| FL4SHK | also, is there an option I need to set to make interfaces actually, uh, compile? | 23:58 |
| FL4SHK | compile correctly* | 23:59 |
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