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| corecode | m | 12:00 |
|---|---|---|
| corecode | oups | 12:00 |
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| FL4SHK | It appears that yosys doesn't know about SystemVerilog interfaces used on ports. Oh well. | 13:25 |
| corecode | yea i had to go back to plain verilog | 13:35 |
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| FL4SHK | corecode: Give me a while (at least a few more months). I'm developing a compiler thing for a SystemVerilog-like HDL that will just spit out Verilog. | 22:01 |
| FL4SHK | Actually, I think it'll spit out yosys-compatible SystemVerilog. | 22:03 |
| FL4SHK | Perhaps not | 22:03 |
| FL4SHK | I'll have it spit out Verilog. | 22:03 |
| FL4SHK | Oh, and I mean it'll be similar to synthesizable SystemVerilog. | 22:05 |
| FL4SHK | I don't know how I'd convert the dynamic stuff to Verilog (strings, handle-based classes, dynamic arrays, etc.) | 22:05 |
| FL4SHK | ... and I've chosen to unify code block syntax: everything is {} | 22:06 |
| FL4SHK | Concatenation looks like a function :P | 22:06 |
| FL4SHK | concat(a, b) | 22:06 |
| FL4SHK | I also cut out a lot, I guess. | 22:07 |
| FL4SHK | But not much of any interest to synthesizing into FPGA code | 22:07 |
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