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| FL4SHK | There is a VHDL frontend for yosys in development, isn't there? | 00:33 |
|---|---|---|
| FL4SHK | wh | 00:40 |
| FL4SHK | I just... saw something in Yosys | 00:40 |
| FL4SHK | SystemVerilog interfaces are supported?! | 00:40 |
| FL4SHK | packages are supported? | 00:41 |
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| mithro | ZipCPU: you should join #symbiflow - Your ears should be burning :-) | 16:41 |
| bubble_buster | any other good related channels? I'm already in ##openfpga as well | 16:50 |
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| ZipCPU | ##verilog? ##dsp #cpudev | 18:09 |
| ZipCPU | There's an #openrisc channel, and a #risc channel too, but they've been somewhat quiet | 18:09 |
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| FL4SHK | Well, I tried synthesizing SystemVerilog interfaces with yosys. | 21:26 |
| FL4SHK | ...It seemed sketchy? | 21:26 |
| FL4SHK | Mostly because I tried ports, I guess | 21:27 |
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