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| promach | Does yosys support systemverilog "inside" keyword yet ? | 02:57 |
|---|---|---|
| promach | seems like yosys does not support fully "inside" keyword, same problem here with https://www.xilinx.com/support/answers/64777.html | 03:00 |
| tpb | Title: AR# 64777: Vivado Synthesis - System Verilog case inside range expression support (at www.xilinx.com) | 03:00 |
| promach | daveshah : have you encountered such situation previously ? | 03:17 |
| promach | I have set up a small test code that illustrates the problem | 03:21 |
| promach | https://www.reddit.com/r/yosys/comments/b0vaml/system_verilog_case_inside_range_expression/ | 03:21 |
| tpb | Title: System Verilog case inside range expression support : yosys (at www.reddit.com) | 03:21 |
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| somlo | daveshah: the trellis versa5g soc example gets a 50MHz clock with the non-default (w.r.t. yosys/ecp5/cells_bb.v) settings of .CLKI_DIV(2), .CLKOP_DIV(12), .CLKOP_CPHASE(11). For a 10MHz clock (for the rocket chip), you got Diamond to come up with .CLKI_DIV(10), .CLKOP_DIV(65), .CLKOP_CPHASE(64). | 12:37 |
| somlo | Turns out, on a *real* 5g ecp5 the rocket chip can go as fast as 24MHz. I get CLKI_DIV (would need 5 for 20MHz), but what about CLKOP_DIV and CLKOP_CPHASE? | 12:37 |
| somlo | ecppll generates 10 and 50 MHz pll settings that are pretty radically different from the working ones we're currently using, so I'm wondering if there's just more than one canonical way to set the pll to generate a given frequency, or what... | 12:38 |
| daveshah | There are different feedback path options, which are the main difference | 12:38 |
| daveshah | The important thing is to keep the VCO in its 400-800MHz range | 12:39 |
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| somlo | ecppll also generates different ICP_CURRENT and LPF_RESISTOR values (12, 8) vs. what's in the working examples (6, 16) respectively. Should I worry about that ? :) | 13:01 |
| sxpert | damned, things that work in simulation, and miserably fail on chip | 13:04 |
| daveshah | No one has figured out the algorithm to determine those values ye5 | 13:27 |
| daveshah | *yet | 13:27 |
| daveshah | They don't seem to be critical, just optimising lock time and jitter I think | 13:27 |
| somlo | so the 20MHz clock as generated by ecppll seems to work (blinking twice as fast now :) ) | 13:28 |
| somlo | nextpnr *sometimes* meets >= 24 MHz, but not always, so I think I'll stick with 20 for now... | 13:29 |
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| MoeIcenowy | somlo: I think you can try to run a for loop to get nextpnr to try to meet 24MHz ;-) | 17:33 |
| tnt | (changing the seed ...) | 17:33 |
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| somlo | MoeIcenowy: if at first you don't succeed... :D | 18:06 |
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| MoeIcenowy | I remember the Supra tool from AGM have such a function to run for a loop to reach timing | 18:19 |
| tnt | Multi Pass Place and Route is/was in Xilinx tools as well. | 18:20 |
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| corecode | i should install trellis and figure out how fast my cpu can run on an ecp5 | 21:36 |
| sxpert | mine looks like it can do 50MHz easily, on the good compilation days | 21:50 |
| corecode | and on the ice40? | 21:51 |
| sxpert | haven't tried for a while | 21:51 |
| corecode | ok | 21:51 |
| sxpert | need to update the script | 21:51 |
| sxpert | at this time it wouldn't fit in the ice40, am using up all of the brams for rom and ram ;-) | 21:52 |
| corecode | chubby | 21:52 |
| sxpert | that is 192 of them ;-) | 21:52 |
| sxpert | and only 1/2 the system rom ;( | 21:52 |
| sxpert | last run, 36Mhz prior to routing, 65.66 after | 21:53 |
| corecode | wow, it sped up | 21:53 |
| sxpert | yeah, it moves randomly | 21:53 |
| sxpert | with me adding stuff ;-0 | 21:54 |
| sxpert | been re-writing from march 6, had some wierd behavior that I couldn't fix | 21:54 |
| corecode | so i want to build a generic debug adapter, which means mostly bit wiggling in different ways, and different control flows; i wonder whether i should try to avoid a mcu and do it in fpga | 21:55 |
| sxpert | so, branched from there, and slowly re-adding the bits from master | 21:55 |
| sxpert | ok, time to head to bed | 21:57 |
| sxpert | enough hadking for the night | 21:57 |
| sxpert | ah no, one more thing I need to check | 21:58 |
| sxpert | then commit and push | 21:58 |
| sxpert | compiling the design takes a good 10mn | 21:59 |
| sxpert | damnit | 21:59 |
| daveshah | sxpert: did you try the new placer? | 22:02 |
| sxpert | daveshah: nope | 22:02 |
| sxpert | is it out yet ? | 22:02 |
| daveshah | It's still not upstream | 22:02 |
| daveshah | But on a pull request | 22:03 |
| sxpert | ah | 22:03 |
| daveshah | https://github.com/YosysHQ/nextpnr/pull/219 | 22:03 |
| tpb | Title: HeAP-based analytical placer by daveshah1 · Pull Request #219 · YosysHQ/nextpnr · GitHub (at github.com) | 22:03 |
| sxpert | how does it apply to a head tree ? | 22:04 |
| corecode | nice | 22:05 |
| daveshah | git remote add daveshah1 https://github.com/daveshah1/nextpnr && git pull daveshah1 && git checkout placer_heap | 22:06 |
| tpb | Title: GitHub - daveshah1/nextpnr: nextpnr portable FPGA place and route tool (at github.com) | 22:06 |
| daveshah | Should do it | 22:06 |
| sxpert | then make clean && make | 22:08 |
| daveshah | Yes | 22:10 |
| daveshah | You'll also need to install eigen3 | 22:10 |
| daveshah | libeigen3-dev on ubuntu | 22:11 |
| sxpert | ok, installed just in time before it has a chance to barf ( while it is building chipdb-85k.bba ;-) ) | 22:12 |
| sxpert | ah, latest run 69.00 MHz | 22:12 |
| sxpert | I only removed a couple ifs that were doing the same thing ! | 22:13 |
| corecode | if they do the same thing, they get optimized away | 22:13 |
| sxpert | somehow something did something different ;-) | 22:13 |
| daveshah | Most likely enough to change ordering of nets and cells, if nothing else | 22:14 |
| daveshah | That will result in a totally different initial placement | 22:14 |
| sxpert | I see | 22:15 |
| sxpert | so it's mostly random, there's no method to this madness ;-) | 22:15 |
| sxpert | ok, so baseline nextpnr generate something that is verified to work | 22:17 |
| daveshah | You can always peturb the placement and routing with the --seed parameter to nextpnr | 22:18 |
| sxpert | daveshah: according to the pr page, there is still an issue compiling on ubuntu 16.04 | 22:18 |
| daveshah | No, that's a regression test failure | 22:19 |
| sxpert | ah | 22:19 |
| daveshah | It's a design that fails sometimes on master too | 22:19 |
| sxpert | ah ! | 22:20 |
| daveshah | The test needs looking at properly | 22:20 |
| sxpert | somehow at the limits of whatever it's trying to do ? | 22:20 |
| daveshah | Yes | 22:20 |
| sxpert | ah the test is somewhat b0rk, that will do it ;) | 22:20 |
| sxpert | sometimes it fits in, sometimes it randomly can't | 22:21 |
| sxpert | I see | 22:21 |
| somlo | re. PR #219, if any of you have a Fedora box laying around this is what I'm using: http://www.contrib.andrew.cmu.edu/~somlo/nextpnr-rpm/ | 22:35 |
| tpb | Title: Index of /~somlo/nextpnr-rpm (at www.contrib.andrew.cmu.edu) | 22:35 |
| * sxpert hopes to never have to run yosys and nextpnr on his Sparcstation V ;-) | 22:39 | |
| * sxpert also hopes nobody attempts a port on vax ;-) | 22:40 | |
| sorear | mm? | 22:48 |
| sxpert | it takes like 30mn to compile on a 4 cores laptop with 16G of ram ;-) | 22:52 |
| sxpert | and your average design take 10mn or so on the same machine | 22:52 |
| sxpert | now imagine on a 1MHz vax ;-) | 22:52 |
| FL4SHK | yes, formally verify on a 1 MHz machine | 22:53 |
| sxpert | hahaha | 22:53 |
| sxpert | insert <2000 years later> card from spongebob squarepants | 22:54 |
| FL4SHK | lol | 22:54 |
| FL4SHK | yes | 22:54 |
| FL4SHK | OLD freaking episode | 22:54 |
| sxpert | why does make install rebuilds the bba files ? | 23:04 |
| daveshah | Probably a bug | 23:09 |
| sxpert | daveshah: also it looks like the work is done twice | 23:25 |
| sxpert | ah, looke like "make", followed by "sudo make install" rebuilds everything | 23:28 |
| sxpert | ok, all compiled and installed (including new trellis and yosys) | 23:33 |
| sxpert | daveshah: hmm | 23:36 |
| sxpert | Info: Running simulated annealing placer. | 23:36 |
| sxpert | is there an option I need to pass in ? | 23:36 |
| daveshah | Did it run HeAP first? | 23:37 |
| sxpert | did initial placement, then this one | 23:37 |
| daveshah | Did it print out anything about solving or spreading? | 23:38 |
| sxpert | not that I can see | 23:38 |
| daveshah | Sounds like it didn't build the new placer | 23:39 |
| daveshah | It should be the default for ECP5 | 23:39 |
| sxpert | nextpnr-ecp5 -- Next Generation Place and Route (git sha1 4c73061) | 23:39 |
| sxpert | is the version I have | 23:39 |
| daveshah | Can you post the full --help | 23:40 |
| sxpert | https://pastebin.com/zp4LDfhs | 23:41 |
| tpb | Title: nextpnr-ecp5 -- Next Generation Place and Route (git sha1 4c73061) General op - Pastebin.com (at pastebin.com) | 23:41 |
| FL4SHK | yosys doesn't do place and route, does it? | 23:41 |
| cr1901_modern | no | 23:42 |
| daveshah | sxpert: there should be some new options, including --sa-placer to switch to the old placer, in there | 23:42 |
| FL4SHK | ...I've only used yosys for formal verification myself | 23:42 |
| sxpert | daveshah: should I have re-run configure or whatever it is ? | 23:43 |
| daveshah | sxpert: rerunning CMake shouldn't be needed in this case | 23:43 |
| daveshah | It certainly wouldn't cause this problem | 23:43 |
| daveshah | What does is the last commit in git log in nextpnr | 23:43 |
| sxpert | ah | 23:43 |
| sxpert | placer1: Only get criticalities when in timing-driven mode | 23:43 |
| sxpert | I notice | 23:44 |
| sxpert | A CMake option 'BUILD_HEAP' (default on) configures building of the | 23:44 |
| sxpert | HeAP placer and the associated Eigen3 dependency. | 23:44 |
| daveshah | Commit sounds correct | 23:44 |
| daveshah | That option is default on, so it should be fine | 23:44 |
| daveshah | Even if it was turned off, that command line help still isn't correct | 23:45 |
| sxpert | ok | 23:47 |
| sxpert | well, bedtime here | 23:47 |
| sxpert | see you tomorrow | 23:47 |
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