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| emeb_mac | question on nextpnr-ice40: trying to use an instance of SB_PLL40_CORE with reference clock originating on-chip in the 48MHz HF osc. Yosys runs OK but nextpnr gives me an error: ERROR: PLL 'pll_inst' couldn't be placed anywhere, no suitable BEL found. | 05:20 |
|---|---|---|
| emeb_mac | This is on a up5k design with clock originating on-chip (not coming from an IO pad) | 05:21 |
| emeb_mac | (reference clock that is) | 05:21 |
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| corecode | hm, why can't it place it | 10:51 |
| tnt | I made a test case and it works for me. | 10:59 |
| tnt | So I'm waiting from him to come back and post a snippet of what he's doing ... | 11:00 |
| corecode | yea | 11:05 |
| daveshah | maybe pin 35 is being used and blocking the pll | 11:09 |
| tnt | Oh yeah, right, that's probably it. | 11:12 |
| corecode | say what? | 11:12 |
| daveshah | certain pins can only be used as outputs when the pll is used | 11:12 |
| tnt | PLL input path is shared with the IO input path of the IO tile it's in. | 11:12 |
| corecode | so the pll is a padin, not a gbufin? | 11:13 |
| daveshah | yes | 11:13 |
| corecode | already forgot again | 11:13 |
| corecode | that seems dumb | 11:13 |
| daveshah | likewise PLLOUTCORE{A,B} use the D_IN_0s of the IO tile they are in | 11:13 |
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| emeb | Just read the channel log - saw the advice on pin 35 vs PLL. Thanks for that - I'll check if moving I/O around in the .pcf helps. | 16:33 |
| emeb | Yes - I did have pin 35 defined as input and freeing it up allowed the PLL to be placed. | 16:40 |
| emeb | Unfortunately, I'm using a upduino V1 for this test and the mistakes in the board design WRT the PLL supply seem to be preventing it from working. | 16:48 |
| emeb | Well, I've got my own boards waiting to be built with proper PLL supply ckts. Will have to wait for those. | 16:49 |
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| tnt | emeb: if you have a bit of wire, you can 'fix' it :p | 16:55 |
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| emeb | tnt: yeah, I could. but, #effort. :) | 17:00 |
| emeb | lol - routed the PLL clock output to a pin and put it on the 'scope. | 17:02 |
| emeb | such jitter! | 17:02 |
| tnt | oh really ? I guess it's not locked right ? | 17:03 |
| MoeIcenowy | I think the internal OSC itself is weird | 17:03 |
| MoeIcenowy | upduino v1... weird board | 17:04 |
| MoeIcenowy | it's even worse than designing one by yourself | 17:04 |
| MoeIcenowy | (recently I purchased a UPduino before I started my own UP5K board, and received it after finished the sample | 17:05 |
| MoeIcenowy | (then I regretted to purchase the UPduino | 17:05 |
| MoeIcenowy | although it's v2 | 17:05 |
| emeb | I'm trying to make a 16 MHz clock from the on-board 48MHz with the PLL. The actual output freq is about 1.2MHz and very wiggly. | 17:05 |
| MoeIcenowy | emeb: why not use DIV? | 17:05 |
| MoeIcenowy | 16 = 48 / 3 | 17:05 |
| MoeIcenowy | add #(.CLKHF_DIV("0b10")) to the SB_HFOSC | 17:06 |
| tnt | MoeIcenowy: I think div only does 48 24 12 6 ... | 17:08 |
| emeb | correct | 17:08 |
| emeb | 16 is not an option | 17:09 |
| emeb | I actually have a /3 circuit stubbed in for now | 17:09 |
| corecode | that hfosc is probably not very good | 17:09 |
| emeb | but only 33% duty cycle, so I wanted to try the PLL | 17:09 |
| corecode | looked jittery to me | 17:09 |
| MoeIcenowy | oh forgot it | 17:09 |
| MoeIcenowy | how to mod my brain to have an ECC memory? | 17:10 |
| corecode | more system 2 | 17:10 |
| corecode | operate as if you are likely to make mistakes | 17:11 |
| emeb | 16MHz output derived from 48MHz HFOSC -> https://www.dropbox.com/s/uepvq6533mmj8jx/0313191108.jpg?dl=0 | 17:20 |
| tpb | Title: Dropbox - 0313191108.jpg (at www.dropbox.com) | 17:20 |
| emeb | (apologies for shakycam) | 17:21 |
| emeb | but yeah - very jittery. | 17:21 |
| MoeIcenowy | emeb: what board? | 17:21 |
| emeb | upduino | 17:21 |
| emeb | only ~45dB down skirts @ 100kHz. nasssty. | 17:24 |
| MoeIcenowy | v1 or v2? | 17:24 |
| emeb | v1 | 17:24 |
| MoeIcenowy | the PLL supply of v1 is quite weird | 17:24 |
| emeb | well, it's just plain wrong and I can't get the PLL to lock. This pic is just the HFOSC | 17:25 |
| emeb | no PLL | 17:25 |
| MoeIcenowy | emeb: how about raw 48MHz output? | 17:28 |
| emeb | wouldn't expect it to be any different. Dividers don't alter jitter. | 17:30 |
| emeb | Here's the direct output from the 48MHz HFOSC with a bit more processing on it: https://www.dropbox.com/s/wz573a9h5p9bxud/0313191128.jpg?dl=0 | 17:37 |
| tpb | Title: Dropbox - 0313191128.jpg (at www.dropbox.com) | 17:37 |
| emeb | averaging on for smoother skirts - about 30dB down @ 100kHz offset | 17:37 |
| emeb | correction - 200kHz offset | 17:39 |
| MoeIcenowy | if I have an oscilloscape I will try to do the experiment on UPduino2 and iCECream v1 | 17:46 |
| tnt | iCECream ? didn't know that one. | 17:46 |
| MoeIcenowy | it's my own board ;-) | 17:49 |
| MoeIcenowy | only 3 fully-installed ones exist on the world ;-) | 17:50 |
| tnt | Ah I see :) | 17:50 |
| MoeIcenowy | in fact it's available on my github | 17:50 |
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| ylamarre | This whole project should just be renamed icepun or icywhatyoudid.... | 18:26 |
| * shapr snickers | 18:28 | |
| ylamarre | You shouldn't give this proposition the cold shoulder... | 18:28 |
| ylamarre | Or are you just having cold feet? | 18:28 |
| shapr | The name symbioyosys got a laugh from me first time I saw it. | 18:28 |
| ylamarre | Ok, symbioyosys is actually pretty good. | 18:29 |
| sorear | did you misspell symbiyosys or are you making a deeper joke I don't get | 18:30 |
| ylamarre | I followed shapr's spelling... | 18:31 |
| shapr | sorear: I got the spelling wrong, sorry | 18:32 |
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| sxpert | it's a nice pun on symbiosis, obviously | 19:49 |
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| elms | Looking for some details on iCE40 IE/REN and ColBufCtrl. Is this the best place to ask (I know it's more icestorm than yosys)? If there is a document with more details I can start there. | 20:44 |
| daveshah | elms: http://www.clifford.at/icestorm/io_tile.html | 20:45 |
| tpb | Title: Project IceStorm IO Tile Documentation (at www.clifford.at) | 20:45 |
| daveshah | this is indeed the usual channel for icestorm stuff BTW :) | 20:45 |
| elms | daveshah: I'd like to expand on that. Some IEREN control bits aren't in the ieren_db. why? Are they just never connected to package pins? | 20:46 |
| daveshah | Yes, some possible locations are not bonded out in any package | 20:46 |
| daveshah | I have a suspicion that there isn't even a pad in some cases | 20:46 |
| elms | ok, but that's why they aren't in the table? | 20:47 |
| daveshah | Yes | 20:47 |
| daveshah | It wouldn't even be possible to fuzz them | 20:47 |
| elms | daveshah: For ColBuf are they there for lower power? If I understand, if they are all enabled, it will just draw more power. | 20:48 |
| daveshah | Yes, it is perfectly safe to enable them all, always | 20:48 |
| elms | daveshah: as always thanks for bringing clarity. | 20:49 |
| daveshah | No problem | 20:50 |
| tnt | Wasn't somebody supposed to decap and take UP5k dieshots ? I saw some 'preview' on twitter but never the full detailled set. | 20:54 |
| daveshah | It was Adam McCombs @nanographs | 20:57 |
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