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| corecode | wow, on the ecp5 my cpu also only does 44MHz | 02:16 |
|---|---|---|
| corecode | i guess i have a shit design | 02:16 |
| sorear | what are you comparing to? what's your goal? | 02:23 |
| corecode | comparing to u4k | 02:24 |
| corecode | where i get 29MHz | 02:24 |
| corecode | sorear: my goal is to improve my design :) | 02:24 |
| sorear | rough specs ? critical path ? | 02:24 |
| corecode | seems to be related to instruction fetch going through some MUXes | 02:26 |
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| emeb_mac | corecode: have you tried checking the max freq of your CPU design using icecube? | 03:16 |
| emeb_mac | (just for comparison to FOSS tools) | 03:17 |
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| daveshah | corecode: switching to the faster ECP5 (normal -8 speed grade or 5G variant) should make a big difference | 09:09 |
| daveshah | The tools for the ECP5 aren't as optimised yet either | 09:09 |
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| sxpert | daveshah: ok. manage to get the placer to compile. had to redo the CMake | 10:18 |
| sxpert | daveshah: ok, it seems to work as advertised. design is even faster than before | 10:25 |
| daveshah | Yeah, the new placer does tend to improve ECP5 quality of results | 10:27 |
| sxpert | hmm | 10:27 |
| sxpert | looks like the generated bitfile doesn't work though | 10:27 |
| * sxpert tries again | 10:27 | |
| daveshah | Sounds like something marginal might be going on | 10:29 |
| sxpert | ah, getting "2 warnings, 1 error" | 10:32 |
| sxpert | ERROR: unsupported frequency unit 'MHZ' | 10:32 |
| sxpert | and | 10:33 |
| sxpert | Warning: ignoring unsupported LPF command 'BLOCK RESETPATHS' | 10:33 |
| sxpert | Warning: ignoring unsupported LPF command 'BLOCK ASYNCPATHS' | 10:33 |
| daveshah | The warnings don't matter | 10:34 |
| sxpert | the error however ? | 10:34 |
| daveshah | The frequency bug was fixed on master but not merged into that branch | 10:34 |
| daveshah | Just change MHZ to MHz | 10:34 |
| * sxpert tries again | 10:36 | |
| sxpert | tons of "Unmatched LPF" warnings, but I suppose that's because I don't use them | 10:40 |
| sxpert | no more errors | 10:40 |
| sxpert | lets program the thing in the chip | 10:41 |
| sxpert | ok, it now works | 10:41 |
| sxpert | does what it should | 10:42 |
| sxpert | good | 10:42 |
| daveshah | The unmatched warnings are also solved in master | 10:44 |
| daveshah | Out of curiosity, what freq are you getting now? | 10:44 |
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| sxpert | hah, looks like we will get rectangles, no more fpga art | 10:48 |
| sxpert | Info: Max frequency for clock '$glbnet$clk_25mhz': 70.67 MHz (PASS at 25.00 MHz) | 10:51 |
| sxpert | before routing : | 10:51 |
| sxpert | Info: Max frequency for clock '$glbnet$clk_25mhz': 40.46 MHz (PASS at 25.00 MHz) | 10:51 |
| daveshah | Yeah, the pre routing delay estimates need tuning | 10:52 |
| daveshah | 70MHz is pretty good, what was it before | 10:53 |
| sxpert | 65 or so | 10:53 |
| sxpert | the design seems pretty fast for such a complicated beast | 10:53 |
| sxpert | still complains about the rom_data | 10:54 |
| sxpert | though | 10:54 |
| daveshah | Yeah, part of the problem is just ECP5 BRAMs being fairly slow - combined with such a big RAM being spread all around the chip | 10:56 |
| daveshah | The BRAMs on the ECP5-5G parts are about 3x faster than the -6 grade normal past | 10:56 |
| daveshah | *parts | 10:56 |
| sxpert | am about to add some more, hah ! | 10:56 |
| sxpert | I have to add 64 BRAMs for the system ram | 10:57 |
| daveshah | Unlikely to make the design any slower - each clocked RAM starts a new timing path, so to say | 10:57 |
| sxpert | right | 10:58 |
| daveshah | It would be interesting to see how making the main ROM smaller changed Fmax | 10:58 |
| sxpert | well, the main issue is that the rom jumps to 7xxxx on the 11th instruction ;-) | 11:05 |
| daveshah | It doesn't need to work | 11:09 |
| daveshah | would just be interesting to see how it changes things... | 11:09 |
| sxpert | ah I see | 11:10 |
| sxpert | just a compile | 11:11 |
| sxpert | I can probably do that | 11:11 |
| sxpert | say, 1 bram worth ? | 11:12 |
| daveshah | yeah | 11:13 |
| sxpert | ok so 1 bram is 16Kb, that's 2**12 nibbles | 11:16 |
| sxpert | I have the system ram in, all 64 brams of it | 11:17 |
| sxpert | and 1 bram for rom | 11:17 |
| sxpert | daveshah: the next thing I want to tackle is the debugger string generation, seems suboptimal, generate ffs instead of brams | 11:19 |
| daveshah | sxpert: sure, where is the code for that | 11:19 |
| sxpert | https://github.com/sxpert/hp-saturn/blob/fix_rom_read/saturn_debugger.v | 11:19 |
| tpb | Title: hp-saturn/saturn_debugger.v at fix_rom_read · sxpert/hp-saturn · GitHub (at github.com) | 11:19 |
| sxpert | here | 11:19 |
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| daveshah | sxpert: I'm afraid that's a bit ambitious | 11:21 |
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| sxpert | ah | 11:21 |
| daveshah | an intermediate write data and write enable register would be more likely to work | 11:21 |
| sxpert | hah ! | 11:21 |
| sxpert | so have an 8 bit byte reg, and write to the memory in another domain ? | 11:22 |
| daveshah | yeah | 11:22 |
| sxpert | with only one rom bram, I get Info: Max frequency for clock '$glbnet$clk_25mhz': 75.16 MHz (PASS at 25.00 MHz) | 11:23 |
| daveshah | Is the critical path still the ROM? | 11:24 |
| * sxpert added the sysram | 11:24 | |
| sxpert | lessee | 11:24 |
| sxpert | daveshah: I get this : https://pastebin.com/sqRb589G | 11:29 |
| tpb | Title: Info: Critical path report for clock '$glbnet$clk_25mhz' (posedge -> posedge): - Pastebin.com (at pastebin.com) | 11:29 |
| daveshah | Looks like system RAM has taken over now | 11:29 |
| sxpert | yeah | 11:29 |
| daveshah | (26,82) -> (27,27) is a long wire | 11:29 |
| sxpert | I see | 11:30 |
| sxpert | guess I could use some registers or something | 11:30 |
| daveshah | yeah | 11:30 |
| sxpert | on reading and writing | 11:31 |
| sxpert | for the rom, I pre-read on phase 0, then dump that on phase 1 to the bus | 11:31 |
| sxpert | guess I could do the same for the ram | 11:31 |
| corecode | ah, it was 44 pre route, 61 post route | 11:33 |
| corecode | and with -8 68 pre route, 85 post route | 11:33 |
| daveshah | that makes much more sense | 11:34 |
| daveshah | what if you try a 5g part (--um5g-45k) | 11:34 |
| daveshah | they have much faster block RAMs | 11:34 |
| corecode | i thought they're all the same die | 11:35 |
| corecode | oh yea | 11:35 |
| corecode | 120 pre, 120 post | 11:35 |
| daveshah | the 5g parts run at 1.2V rather than 1.1V | 11:35 |
| * sxpert would love an ULX3S++ with an 85FUM5G ;-) | 11:35 | |
| daveshah | this makes a big difference | 11:35 |
| corecode | aha! | 11:35 |
| sxpert | 47€ a piece on mouser ! | 11:39 |
| sxpert | not too bad | 11:40 |
| sxpert | the evn board is 86 eur | 11:40 |
| daveshah | yeah, the evn board is very good value for money | 11:40 |
| daveshah | only problem is it has no external RAM :( | 11:40 |
| sxpert | hah | 11:41 |
| sxpert | that's a problem | 11:41 |
| sxpert | all depends on the system flash though. I could do with the system rom in the flash | 11:50 |
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| sxpert | daveshah: ok, ram accesses are now pipelined | 13:26 |
| sxpert | Info: Max frequency for clock '$glbnet$clk_25mhz': 72.06 MHz (PASS at 25.00 MHz) | 13:26 |
| sxpert | rom still shows up as the biggest delay | 13:26 |
| sxpert | not a big issue though | 13:27 |
| daveshah | what does --um5g-85k give? | 13:28 |
| daveshah | I guess this is much faster than a real Saturn? | 13:28 |
| sxpert | the real saturn ran at 4MHz | 13:31 |
| sxpert | also, I seem to be able to implement things in less cycles than the original | 13:32 |
| daveshah | Could you make an upgrade board for calculators with an ECP5 on? | 13:32 |
| sxpert | possibly | 13:32 |
| daveshah | Might need a bigger battery too | 13:32 |
| daveshah | that would be really awesome | 13:32 |
| sxpert | yeah | 13:32 |
| sxpert | replace those 3x AA with lipo | 13:32 |
| sxpert | or was it AAA | 13:32 |
| sxpert | yeah, 3x AAA | 13:32 |
| sxpert | blast the TIs out the water ;) | 13:33 |
| sxpert | the original idea was to build one with a giant led screen | 13:34 |
| sxpert | so, with all basic modules setup, am going at 70Mhz or so | 13:36 |
| sxpert | (rom, mmio, ram) | 13:36 |
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| sxpert | now, just need to fill in alu based instructions | 13:37 |
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| sxpert | daveshah: on the um5g-85k part: Info: Max frequency for clock '$glbnet$clk_25mhz': 108.05 MHz (PASS at 25.00 MHz) | 14:00 |
| daveshah | Nice | 14:01 |
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| MoeIcenowy | daveshah: I think a Saturn emulator on ARM920T is faster than real Saturn | 14:21 |
| MoeIcenowy | (I have such an emulator | 14:21 |
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| sxpert | MoeIcenowy: indeed, an emulator on an arm is faster, but it's not the same thing | 14:29 |
| sxpert | for instance, you can't do grayscale display | 14:30 |
| sxpert | also, that's no fun ;) | 14:31 |
| sxpert | the fun part is, I may also implement the instruction added in that emulator ;-) | 14:37 |
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| sxpert | (all those 80Cblah instructions) | 14:42 |
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| MoeIcenowy | sxpert: I only bought a 39gs because it's dirty cheap | 15:36 |
| MoeIcenowy | sxpert: in fact I wonder why don't they add some "execute raw ARM code" instruction ;-) | 15:41 |
| somlo | daveshah: is there a branch on github for the "stable" trellis? (https://twitter.com/fpga_dave/status/1101216373454393349) Do you have version numbers anywhere that I should "bump" (from "0.0") before I open a bugzilla ticket for submitting to Fedora ? | 15:52 |
| daveshah | somlo: It's a git tag, 1.0 | 15:53 |
| somlo | oh, so I'll actually have to clone the repo before I can see it :) Thanks! | 15:53 |
| daveshah | You can get it on github too | 15:54 |
| daveshah | https://github.com/SymbiFlow/prjtrellis/tree/1.0 | 15:54 |
| tpb | Title: GitHub - SymbiFlow/prjtrellis at 1.0 (at github.com) | 15:54 |
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| sxpert | MoeIcenowy: there is | 16:20 |
| sxpert | MoeIcenowy: the main issue with those is that the keyboard is chicklet and pretty bad | 16:21 |
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| MoeIcenowy | daveshah: BTW why does icestorm have no version number? | 17:28 |
| daveshah | idk | 17:29 |
| daveshah | getting clifford to do proper releases is always hard | 17:29 |
| ZipCPU | ;) | 17:30 |
| sxpert | heh | 18:24 |
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| somlo | fedora review request for trellis: https://bugzilla.redhat.com/show_bug.cgi?id=1689397 | 19:59 |
| tpb | Title: 1689397 Review Request: trellis - Lattice ECP5 FPGA bitstream creation/analysis/programming tools (at bugzilla.redhat.com) | 19:59 |
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| sorear | gonna try to get that in #fedora-riscv? :D | 20:02 |
| somlo | yeah, that's the plan -- find/buy (or, worst case, design/build) a dev board with 2GB RAM and an 85k 5g ECP5 chip, build a rv64gc based SoC that can boot Fedora (similar to lowRISC), then we'd have a self-hosting computer (that can not only rebuild its own kernel, but also its own *hardware*) :) | 20:06 |
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| sxpert | somlo: can you self-update the flash and reboot the fpga ? | 21:06 |
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| somlo | sxpert: I think that depends on the particulars of the (at this point, theoretical) development board | 22:49 |
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