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tnt | Is there anyway to make yosys search the parent verilog file directory for includes and not just the explicit -I path and the cwd ? | 20:16 |
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tnt | Oh wait ... it might be doing that already. | 20:21 |
emeb | the thing that always gets me is the path to search for $readmem files - every EDA tool handles it differently so I always have to guess where to put them. | 20:34 |
tnt | Yeah that's my next thing to work out ... | 20:38 |
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corecode | emeb: they search in the current directory, but often that is where the auto-generated project file is | 21:03 |
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emeb | corecode: right - and on icecube for example it's hard to figure out where in the dir tree that is, so I end up having to guess how many "../../.." to put in the file name. | 21:22 |
emeb | would be nice if they'd just assume the mem files are in the same dir as the .v files. | 21:23 |
emeb | or give an option like for includes and libs | 21:23 |
corecode | yea readmemb should be relative to the source location | 21:35 |
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