Wednesday, 2019-03-06

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tnt Is there anyway to make yosys search the parent verilog file directory for includes and not just the explicit -I path and the cwd ?20:16
tntOh wait ... it might be doing that already.20:21
emebthe thing that always gets me is the path to search for $readmem files - every EDA tool handles it differently so I always have to guess where to put them.20:34
tntYeah that's my next thing to work out ...20:38
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corecodeemeb: they search in the current directory, but often that is where the auto-generated project file is21:03
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emebcorecode: right - and on icecube for example it's hard to figure out where in the dir tree that is, so I end up having to guess how many "../../.." to put in the file name.21:22
emebwould be nice if they'd just assume the mem files are in the same dir as the .v files.21:23
emebor give an option like for includes and libs21:23
corecodeyea readmemb should be relative to the source location21:35
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