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| chaseemory | ZipCPU: Would you happen to know how to program the flash on the nexys video with tcl commands? | 00:13 |
|---|---|---|
| ZipCPU | No | 00:13 |
| ZipCPU | chaseemory: I've never programmed the flash with tcl commands | 00:14 |
| * ZipCPU likes to use his own flash driver | 00:14 | |
| chaseemory | oh nice, i switched to an entirely terminal based FGPA flow at home, after doing the ASIC stuff at school, i probably struggled the most with getting programming to work with a tcl script | 00:15 |
| ZipCPU | Originally, I'd only ever program a board once | 00:16 |
| ZipCPU | Ever after, I'd use that first program to load new configurations | 00:16 |
| ZipCPU | You can find my flash design at http://opencores.org/projects/qspiflash if you are interested | 00:19 |
| tpb | Title: Overview :: Quad SPI Flash Controller :: OpenCores (at opencores.org) | 00:19 |
| chaseemory | huh, it seems to work in sim, the digging must continue | 00:46 |
| ZipCPU | chaseemory: Don't tell me you are getting stuck on my sim/h/w mismatch .. ? | 01:01 |
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| chaseemory | well, it could be... :^) | 01:23 |
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| sxpert | daveshah: why does nextpnr puts things very far apart, or close together sometimes, with no apparent reason ? I'm getting 2 small blobs one on the horizontal center line, and one 1/5th down the top, all on the left side | 06:58 |
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| tnt | sxpert: random initial placement and then randomly moves stuff around to try and improve timing bit by bit. Most likely there is something like a RAM or a DSP or the IOS or something around those points that makes the other logic "attracted" to ti. | 07:55 |
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| keesj | are you guys interested in smaller improvements[tm]? (I am interested in helping out hence tried making a small change and pushing it to the icestorm project https://github.com/cliffordwolf/icestorm/pull/201 but I don't see much happening) | 08:21 |
| tpb | Title: Move icestick examples to their own respective directory. by keesj · Pull Request #201 · cliffordwolf/icestorm · GitHub (at github.com) | 08:21 |
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| ZipCPU | keesj: Does this mean you are using Verilog now? | 12:18 |
| sxpert | tnt: ah, I see. some better initial placement algorigthm would be in order then | 12:19 |
| sxpert | such as, preferably use bram blocks next to each other | 12:19 |
| keesj | ZipCPU: I am in the middle of different projects right now I first need to use migen (to play/tweak https://github.com/enjoy-digital/litedram ) hence .. I am ... not where I really want to be (preffer to learn verilog first but .. that is how it goes). | 12:23 |
| tpb | Title: GitHub - enjoy-digital/litedram: Small footprint and configurable DRAM core (at github.com) | 12:23 |
| keesj | hence.. learning about .v the hard way | 12:24 |
| keesj | https://spinalhdl.github.io/SpinalDoc-RTD/ also looks quite tempting I must say.. but first v | 12:24 |
| tpb | Title: Welcome to SpinalHDL’s documentation! SpinalHDL documentation (at spinalhdl.github.io) | 12:24 |
| keesj | slowwwwly getting there:( | 12:28 |
| tnt | sxpert: in the projects where it matters, I now resorted to manually place those :p | 12:29 |
| sxpert | ah | 12:34 |
| tnt | I think it's a bit inherent to the SA placer that large blocks like RAMs are hard to move because (1) you have few locations (2) since it has lots of connections it's probably hard to find a new location that results in a timing improvement in a single step (i.e. without also moving all the associated logic) and so I'm not sure it's "taken" very often. | 12:40 |
| tnt | (but that's just my crude understanding of SA) | 12:41 |
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| sxpert | %Warning-WIDTH: saturn-decoder.v:447: Operator CASE expects 6 bits on the Case expression, but Case expression's VARREF 'i_nibble' generates 4 bits. | 13:01 |
| sxpert | what does that mean ?? | 13:01 |
| sxpert | i_nibble is indeed 4 bits, and all cases are 4 bits... | 13:02 |
| sxpert | never mind, some typo | 13:03 |
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| promach_ | for yosys-smtbmc, why it does not accept $anyconst to be used for 'parameter' and 'localparam' ? | 14:27 |
| promach_ | ERROR: Failed to detect width for parameter | 14:27 |
| ZipCPU | Yea, ahm ... it doesn't work that way | 14:45 |
| ZipCPU | Remember, promach_, you are designing "hardware" | 14:45 |
| ZipCPU | parameters can be used to specify the number of wires used in a module, register values cannot adjust that later | 14:46 |
| sxpert | ZipCPU: how will something like output reg [3:0] o_mem_load[15:0]; | 15:09 |
| sxpert | be generated ? | 15:09 |
| ZipCPU | It can't be | 15:10 |
| ZipCPU | That's a memory | 15:10 |
| ZipCPU | You can't pass memories through I/O ports | 15:10 |
| sxpert | ah | 15:10 |
| sxpert | ok then | 15:10 |
| ZipCPU | I've sometimes gotten around that by concatenating the items in the memory together, such as output reg[4*15-1:0] o_mem_load; | 15:10 |
| ZipCPU | Internal to the design, you can often then do: for(k=0; k<16; k=k+1) w_mem_load[k] = o_mem_load[k*16 +: 16]; | 15:11 |
| sxpert | ah | 15:11 |
| ZipCPU | Likewise for the same sort of thing in reverse | 15:11 |
| sxpert | that will generate whatever logic is required to unload ? | 15:12 |
| sxpert | k needs to be declared as [4:0] I suppose ? | 15:13 |
| ZipCPU | k is usually declared as either an integer or a genvar | 15:21 |
| ZipCPU | Personally, I like the genvar approach better | 15:21 |
| sxpert | ah | 15:23 |
| * sxpert looks what a genvar is | 15:23 | |
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| sxpert | so, a genvar is a virtual signal that gets used by the for, and disappears in the design. ok | 15:32 |
| sxpert | as I understand it can only be used within the same event | 15:33 |
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| promach_ | What do you guys think about https://gist.github.com/promach/5f2d9a9494704ed93cf65687c982198c ? | 16:52 |
| tpb | Title: A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm · GitHub (at gist.github.com) | 16:52 |
| promach_ | I will work on induction bugs later, just asking for some comments now | 16:53 |
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| ZipCPU | I get lost when I get to line 86 | 16:59 |
| promach_ | ZipCPU: look at line 21 | 16:59 |
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| ZipCPU | Because that makes so much more sense? | 17:00 |
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| promach_ | understanding graphically is easier | 17:01 |
| ZipCPU | Sigh | 17:01 |
| promach_ | huh ? | 17:01 |
| promach_ | I write code based on that picture | 17:01 |
| ZipCPU | Years ago, I remember preparing a presentation for my Ph.D. committee on the work I had done. I had worked hard on it, and was quite proud of it. I had the opportunity to show it to one of my sponsors to get his comments on it. He tore me a new one. His first comment: my graphs had no units on them | 17:02 |
| ZipCPU | He then proceeded to go through my graphics, explaining how they looked like "undergraduate" work because they weren't complete in their descriptions | 17:03 |
| ZipCPU | The picture you recommend on line 21 doesn't even describe the units it is using. It appears to start with binary, but the '2' digit makes no sense within it | 17:03 |
| promach_ | hmm... give me some time to make the code comments clearer | 17:03 |
| promach_ | 2 means two '1' | 17:03 |
| ZipCPU | Not without any explanation | 17:04 |
| promach_ | 1+1 in binary is 10 | 17:04 |
| promach_ | but in the pic, they just use 2 | 17:04 |
| ZipCPU | But 10 is *very* different from 2 | 17:04 |
| promach_ | sorry | 17:04 |
| ZipCPU | So, I'd get torn a new one again for explaining my projects using someone else's pictures | 17:04 |
| promach_ | I will make the comments clearer during the weekend | 17:04 |
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