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| promach_ | ZipCPU: Which part of the code you still do not understand ? I will make them clearer | 01:18 |
|---|---|---|
| corecode | daveshah: do you know how the colbuf_db is made? | 01:21 |
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| corecode | i made + ran a colbuf_io*.sh, but i don't know what i am looking for in the output | 01:21 |
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| corecode | yea i need some assistance figuring out these last bits | 02:38 |
| corecode | unclear where they come from and what the order needs to be | 02:39 |
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| daveshah | corecode: colbuf_logic is probably the most important script. | 08:48 |
| daveshah | You should get four numbers per line | 08:49 |
| daveshah | in each case, x and y of the column buffer and x and y of the global user | 08:49 |
| daveshah | Chances are that x will be the same for both | 08:49 |
| daveshah | So then in icebox.py you are creating a mapping from global user location (the second pair of numbers) to colbuf location (the first pair) | 08:51 |
| daveshah | I think there is also a script to visualise this as an svg | 08:51 |
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| corecode | the script falls on its face tho, because it icebox to already know where the colbuf is | 10:46 |
| corecode | i think | 10:46 |
| daveshah | No, it only needs to know what the colbuf bits are | 11:03 |
| daveshah | They should be the same across devices | 11:03 |
| daveshah | That's different to the tile locations where colbufs are | 11:04 |
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| promach | ZipCPU: Which part of the code you still do not understand ? I will make them clearer. I need your comment because that would make the code more user-readable and user-friendly | 11:49 |
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| sxpert | there is $display, is there a $waitkey function ? | 14:12 |
| ZipCPU | When using Verilator, it's not that hard to build. As I recall, that was one of my tutorial lessons ;) | 14:13 |
| sxpert | ZipCPU: so I rewrote it all again ;) | 14:43 |
| sxpert | yosys finds 669 cells and next-pnr finds 316, is that supposed to be normal ? | 14:46 |
| sxpert | (after all there's 2 lut per cell, so that seems plausible) | 14:46 |
| ZipCPU | sxpert: Yes, that's normal | 14:46 |
| sxpert | ok | 14:47 |
| sxpert | so far, I manage to execute the first 8 instructions of the rom ;) | 14:47 |
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| somlo | daveshah: after prjtrellis commit 72418c7 there's still an explicit basecfg reference in examples/picorv32_versa5g/Makefile; do you want to fix that separately, or should I include it in the rebased PR #59 (where I'm adding "TRELLIS=/usr/share/trellis" to get rid of the remaining openocd relative paths? | 17:11 |
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| tnt | corecode: mm, what are you working on if you don't mind me asking ? | 17:19 |
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| corecode | trying to get ice5lp support in icestorm | 17:25 |
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| tnt | corecode: ah, nice ! I thought that might have been it from the questions, but wanted to double-check :p | 17:29 |
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| daveshah | somlo: feel free to add to your PR | 18:02 |
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| somlo | daveshah: done | 18:10 |
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| keesj | what is the story with https://www.seeedstudio.com/Sipeed-TANG-PriMER-FPGA-Development-Board-p-2881.html?utm_source=mailchimp&utm_medium=edm&utm_campaign=bazaar_0214&mc_cid=bc80ae7c28&mc_eid=54721c1b99 anlogic are they open to providing information? | 20:03 |
| tpb | Title: Sipeed TANG PriMER FPGA Development Board - Seeed Studio (at www.seeedstudio.com) | 20:03 |
| daveshah | micko is working on them: https://github.com/mmicko/prjtang | 20:08 |
| tpb | Title: GitHub - mmicko/prjtang: Documenting the Anlogic FPGA bit-stream format. (at github.com) | 20:08 |
| keesj | thanks daveshah I just found it ! | 20:08 |
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