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| emeb | is it legal to use $readmemh() to define the contents of an ice40 UP BRAM in yosys? | 16:19 |
|---|---|---|
| daveshah | BRAM, but not SPRAM | 16:19 |
| daveshah | there is no way in the bitstream to initialise SPRAM | 16:19 |
| emeb | I understand that | 16:20 |
| emeb | but I've got a testcase where I use $readmemh() to define a ROM and the CPU won't run correctly | 16:20 |
| emeb | but when I do a case() statement with the same data it works fine | 16:20 |
| emeb | https://pastebin.com/HEPr4BSP | 16:21 |
| tpb | Title: //`define USE_BRAM `ifdef USE_BRAM // put code in a pre-loaded block ram - Pastebin.com (at pastebin.com) | 16:21 |
| emeb | either of those two works in iverilog, but only the case() works in hardware | 16:21 |
| daveshah | Are you waiting the requisite ~10µs after startup? | 16:22 |
| emeb | Not explicitly. | 16:23 |
| daveshah | The iCE40 BRAM isn't properly initialised at boot | 16:23 |
| daveshah | you have to wait about 10µs or so for it to work | 16:24 |
| emeb | OK - I've got a 2us reset generator. Can try extending that. | 16:24 |
| daveshah | might be worth trying | 16:26 |
| emeb | Thanks for the heads-up. That's a very "interesting" detail. | 16:26 |
| emeb | daveshah: OK - that seems to have fixed it. Many thanks. | 16:33 |
| sxpert | daveshah: ok, rewrote lots of my code last night | 16:40 |
| sxpert | I am at the point where I have most of my imbricated ifs at 3 levels | 16:41 |
| sxpert | is that too much ? | 16:41 |
| somlo | daveshah: mind rebasing nextpnr PR#219 (it now clashes with commit 565d5ee, and I don't feel qualified to decide how to resolve the conflict myself :) | 16:42 |
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| daveshah | somlo: done | 16:59 |
| daveshah | sxpert: not sure, depends if it meets timing at the end of the day] | 17:00 |
| somlo | daveshah: thanks! | 17:02 |
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| emeb | feeling kinda dumb for not knowing about that 10us startup delay on ice40 BRAM. But quick scanning thru Lattice docs for BRAM and config/startup didn't reveal any obvious documentation for it. Anyone have a reference, or did Lattice just blow it off? | 17:58 |
| daveshah | There's no official reference afaik | 17:58 |
| emeb | sigh | 17:58 |
| daveshah | https://github.com/cliffordwolf/icestorm/issues/76 | 17:59 |
| tpb | Title: Block ram reads within ~36 cycles of device reset always return 0, but only on the first reset after device reconfiguration. · Issue #76 · cliffordwolf/icestorm · GitHub (at github.com) | 17:59 |
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| maikmerten | errata are fun. Undocumented errata are even more fun | 18:02 |
| maikmerten | (depending on your definition of fun) | 18:03 |
| emeb | "teachable moments" | 18:04 |
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| sxpert | daveshah: I have kept this from all the compile runs | 20:52 |
| sxpert | https://github.com/sxpert/hp-saturn/blob/master/history.txt | 20:52 |
| tpb | Title: hp-saturn/history.txt at master · sxpert/hp-saturn · GitHub (at github.com) | 20:52 |
| sxpert | dunno how to interpret it though | 20:53 |
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| ZipCPU | Ok ... my proof is running. Anyone want to chat about what they're up to? | 22:13 |
| ZipCPU | :D | 22:13 |
| chaseemory | im trying to get the ethernet port on my nexys_video working :D | 22:17 |
| ZipCPU | What, you too? | 22:19 |
| ZipCPU | That was my task yesterday | 22:19 |
| ZipCPU | Made a lot of progress at it too | 22:19 |
| chaseemory | https://github.com/alexforencich/verilog-ethernet | 22:19 |
| tpb | Title: GitHub - alexforencich/verilog-ethernet: Verilog Ethernet components (at github.com) | 22:19 |
| ZipCPU | I got to the point where I could read packets, but couldn't write them (yet) | 22:19 |
| chaseemory | I'm trying to use that | 22:20 |
| ZipCPU | https://github.com/ZipCPU/videozip | 22:20 |
| tpb | Title: GitHub - ZipCPU/videozip: A ZipCPU SoC for the Nexys Video board supporting video functionality (at github.com) | 22:20 |
| ZipCPU | chaseemory: Is that your own repository, or someone elses? | 22:20 |
| chaseemory | someone elses | 22:21 |
| chaseemory | I hadnt ever used axi either, so i was reading a few of your articles on it this morning, thinking thats where my hangups were | 22:21 |
| ZipCPU | Heh -- that's today's task, creating a set of formal properties to verify an AXI component | 22:22 |
| ZipCPU | Does his controller run with AXI? | 22:22 |
| * ZipCPU looks for the spec/documentation | 22:22 | |
| chaseemory | yeah it uses AXI-stream throughout | 22:23 |
| ZipCPU | Ok, got it | 22:23 |
| ZipCPU | I used my own streaming protocol when I needed one | 22:23 |
| ZipCPU | I've never tried to verify anything with AXI stream in it so far ... it just looked too easy (Of course, I've never used AXI stream, so I could be pretty wrong there too ...) | 22:24 |
| ZipCPU | chasemory: What speed are you trying to run the port at? | 22:25 |
| chaseemory | gigabit, that repo supports gig or 10gig, not that ill be using all that bandwidth | 22:29 |
| ZipCPU | I ask only because at the end of the day, I was getting a weird hw/sim mismatch. My guess was that the 125MHz clock from the PHY wasn't running at a constant speed. (I was trying to use the receive clock for transmit as well.) | 22:30 |
| chaseemory | i know axi says all the lines need to be registered, but im running all of mine combinatorialy, but only based off the current state, so i thought itd be ok | 22:35 |
| ZipCPU | Ok, well ... is it okay? | 22:36 |
| sxpert | I worked on what I learned yesterday. in particular, reducing the level of if/case imbrications | 22:37 |
| ZipCPU | sxpert: Still on the fence with formal methods? | 22:37 |
| * ZipCPU looks over his proof ... it's still running | 22:38 | |
| sxpert | well, I started reading, but still haven't fully understood the thing | 22:39 |
| ZipCPU | Have you found any of the examples of the counters? | 22:39 |
| ZipCPU | They're good to learn from | 22:39 |
| sxpert | have read this https://zipcpu.com/blog/2017/10/19/formal-intro.html so far | 22:40 |
| tpb | Title: My first experience with Formal Methods (at zipcpu.com) | 22:40 |
| sxpert | (took a while) | 22:40 |
| ZipCPU | There's a better interface to the tools than that article presents | 22:40 |
| ZipCPU | So, when writing a CPU, there tend to be lots of redundancy within the FFs of a design | 22:41 |
| ZipCPU | Hmm ... let me start over | 22:41 |
| ZipCPU | Within a CPU, you have very specific requirements you need to meet. Perhaps the two biggest are 1) the peripheral/memory interface, and 2) that your various instructions do as you expect | 22:42 |
| sxpert | I'll keep 1 for later | 22:42 |
| ZipCPU | The neat thing about 1, though, is that once you do it ... it applies everywhere throughout your design--everywhere you (re)use that basic interface | 22:43 |
| sxpert | I'm currently working on decoding all those instructions to something the thing can use | 22:43 |
| ZipCPU | Yesh, decoders tend to be ugly | 22:43 |
| ZipCPU | Easy to verify, but ugly to code | 22:43 |
| sxpert | well, there's a method to the madness ;) | 22:43 |
| sxpert | in particular with that device, everything more or less goes through the ALU | 22:44 |
| ZipCPU | Risc-V's are even uglier to decode than ... a lot of the other things I've seen | 22:44 |
| ZipCPU | I had a challenge to prove that I had the right registers going into my ALU. Your CPU as I recall is much simpler | 22:45 |
| ZipCPU | I was struggling to deal with interrupts, memory wait states, divide and multiply wait states, etc | 22:45 |
| sxpert | currently, I'm decoding most of it to dest, op, src1, src2, start_nibble, end_nibble | 22:45 |
| ZipCPU | Do all of your instructions fit within one word, or are they multi-byte instruction strings? | 22:45 |
| sxpert | they can be up to 21 4 bits nibble | 22:46 |
| * ZipCPU looks over his proof ... it's still going after step 35, but now up to 30 minutes | 22:46 | |
| ZipCPU | Let's see ... that's up to nearly 10-bytes long? | 22:46 |
| sxpert | 10.5 | 22:47 |
| ZipCPU | That's ugly | 22:47 |
| ZipCPU | Can you at least depend upon a one clock delay from memory when attempting to read instructions? | 22:47 |
| sxpert | longest opcode is LA (Load A), 8082n[n-nibbles] | 22:47 |
| ZipCPU | Load address ... how big is your address space? | 22:48 |
| sxpert | nah, load register A, addresses are 5 nibbles | 22:48 |
| sxpert | registers are 64 bits | 22:48 |
| sxpert | except memory addressing registers that are 20 bits | 22:48 |
| ZipCPU | How many registers? | 22:48 |
| sxpert | A, B, C, D are the main ones, then you have R[0-4] that you can only save into from A or C, then 2 pointers D0 and D1, and some ancillary stuff | 22:49 |
| ZipCPU | So you have several special purpose registers then? | 22:50 |
| sxpert | yeah, there's a 4 bits P register to point at a particular nibble in one of the others | 22:51 |
| sxpert | some status bits, and an 8 level return stack | 22:52 |
| ZipCPU | Only 8 stack entries? | 22:52 |
| sxpert | yeah | 22:52 |
| ZipCPU | 20'bits of memory? Or just a 20'bit address space? | 22:53 |
| sxpert | 20 bits address space, you can configure ram modules to be anywhere in the address space, and move them around as needed | 22:54 |
| ZipCPU | And I think you said that the RAM was guaranteed to respond in one cycle, right? | 22:54 |
| sxpert | well, there's a bus controller that fakes it if required | 22:55 |
| sxpert | (it can stall the cpu if needs be) | 22:55 |
| ZipCPU | Really? What type of bus? | 22:55 |
| ZipCPU | Custom, or well-known? | 22:56 |
| sxpert | between the cpu and the external memory controller is a 4 bits bus, through which things like adresses are sent one nibble at a time | 22:56 |
| ZipCPU | A 64-bit CPU, but with only 4'bits of data bus? | 22:57 |
| ZipCPU | This is a historical CPU, right? | 22:57 |
| sxpert | actual doc is here : http://www.hpmuseum.net/document.php?hwfile=5757 | 22:57 |
| sxpert | yeah, this was designed in sept-1984 | 22:58 |
| daveshah | awesome | 22:58 |
| daveshah | that's a really cool project then | 22:59 |
| sxpert | this thing led to a series of pocket calculators that beat the crap out of Z-80 based casio and TI for a couple decades | 22:59 |
| ZipCPU | Do you know any of the history of that computer? As in, what makes it valuable to you? | 22:59 |
| sxpert | yeah, used those HP calcs since high school | 22:59 |
| ZipCPU | Pocket calculators? Oh, now that starts to get fascinating | 22:59 |
| ZipCPU | Do you know where/how to find any of the ROMs they used? | 23:00 |
| sxpert | yeah, that's the CPU in the HP series | 23:00 |
| sxpert | all roms are available | 23:00 |
| ZipCPU | Nice! | 23:00 |
| sxpert | https://www.hpcalc.org/hp48/pc/emulators/ | 23:00 |
| tpb | Title: HP Calculator Emulators for the PC (at www.hpcalc.org) | 23:00 |
| sxpert | see here | 23:01 |
| sxpert | ROM something | 23:01 |
| ZipCPU | Are you hoping to recreate a whole calculator with it, and run those ROMs? | 23:01 |
| sxpert | yeah | 23:01 |
| ZipCPU | Or do you have other goals? | 23:01 |
| sxpert | make one with a giant led array screen | 23:01 |
| ZipCPU | Sounds like a really cool project | 23:01 |
| * ZipCPU looks at his proof, and starts to think a set of formal AXI properties pales by comparison ;) | 23:02 | |
| sxpert | I believe this CPU was also used in some HP printers of the era | 23:02 |
| ZipCPU | Lineprinters? Desktop printers? Dot-matrix? | 23:02 |
| sxpert | I think their initial inkjet stuff | 23:03 |
| ZipCPU | In '84, wouldn't that have been dot matrix? | 23:03 |
| sxpert | https://en.wikipedia.org/wiki/HP_Saturn | 23:03 |
| tpb | Title: HP Saturn - Wikipedia (at en.wikipedia.org) | 23:03 |
| sxpert | that article says it all ;) | 23:03 |
| sxpert | so the HP thinkjet | 23:04 |
| ZipCPU | That article has a *LOT* of links and tables | 23:04 |
| sxpert | there's a "chipsets and applications" paragraph | 23:04 |
| ZipCPU | Not sure I'd call that a "paragraph" ;) | 23:05 |
| sxpert | well, table then ;) | 23:05 |
| ZipCPU | Let's see ... I bought my first HP calculator in ... was in '95? | 23:06 |
| ZipCPU | (It wasn't a graphing calculator ... ;( | 23:06 |
| sxpert | then that's what's in there ;) | 23:06 |
| sxpert | which one was it ? | 23:06 |
| ZipCPU | Looking for it now ... | 23:07 |
| ZipCPU | The 22S looks familiar | 23:07 |
| ZipCPU | I might have to head upstairs and find out ... | 23:08 |
| ZipCPU | Here it is: the HP-20S | 23:09 |
| ZipCPU | I bought it during a final exam, when I realized afterwards that I needed a calculator for the exam | 23:10 |
| sxpert | saturn it is ;) | 23:10 |
| sxpert | 1LU7, bert ;) | 23:10 |
| ZipCPU | I thought I was buying an RPN calculator. The 20S isn't an RPN calculator. It took me a bit before I was productive with it--all during my final exam | 23:11 |
| sxpert | heh | 23:12 |
| sxpert | and there's that business series that one needs to be careful about ;) | 23:12 |
| ZipCPU | Sounds like you are working on an amazing project. Thanks for sharing! | 23:12 |
| ZipCPU | Why so? | 23:12 |
| sxpert | you mean, the business series ? well they don't do scientific maths ;) | 23:14 |
| ZipCPU | Heh, okay, yeah. I avoided that series | 23:15 |
| ZipCPU | The one I purchased could do a 3x3 matrix inverse ... but there was no way I would've figured out how to do that during that final exam | 23:15 |
| sxpert | heh | 23:17 |
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