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| janrinze | ZipCPU: have you been able to infer the hardware multiplier of up5k with yosys? | 11:38 |
|---|---|---|
| ZipCPU | janrinze: I just tried, and it didn't infer ... let me update my version and see if this was fixed recently at all | 11:42 |
| ZipCPU | With the updated version it still doesn't infer | 11:48 |
| ZipCPU | I'm not sure if this capability has been built into yosys yet. I know I've heard daveshah and clifford discussing how they might add it, but not the results of those conversations | 11:49 |
| janrinze | with BRAM it had a special way of inferring. might there be a thingy for the multiplier too? | 11:50 |
| daveshah | We'll be working on that next year | 11:50 |
| janrinze | daveshah: the BRAM had a special way of explicitly inferring. is there a similar library for the multiplier? | 11:51 |
| ZipCPU | I'm pretty sure you can instantiate the underlying DSP element directly, just never tried doing it. | 11:52 |
| janrinze | ZipCPU: only if i know what the module is called :D | 11:53 |
| daveshah | SB_MAC16 | 11:53 |
| * ZipCPU is checking the yosys/techlibsecp5 directory to see if its there | 11:53 | |
| ZipCPU | SB_MAC16? Is it a 16x16 MAC as opposed to the 18x18 I've gotten used to from Xilinx? | 11:54 |
| janrinze | ZipCPU: yes, all documentation refers to 16x16 | 11:56 |
| ZipCPU | Here it is: techlibs/ice40/cells_sim | 11:57 |
| janrinze | daveshah: I wish there was a way to change only the pll setting after running yosys and nextpnr | 11:59 |
| daveshah | hmm, that shouldn't be too hard a tool to make | 11:59 |
| daveshah | or you could use the PLL SPI to configure it at runtime | 11:59 |
| janrinze | daveshah: would it be okay to set the required bits from say a register and allow it to be rewritten during runtime? | 12:00 |
| janrinze | the SB_PLL40_CORE parameters, can they be registers? | 12:01 |
| daveshah | no, they are bits in the bitstream - the only way to change them at runtime is using the SPI interface (but that isn't really documented) | 12:05 |
| janrinze | the thing is that when i run yosys and nextpnr the end result varies in speed. changing the pll requires another round of yosys and nextpnr and then the speed is not matching anymore. | 12:05 |
| janrinze | okay, the bits in the bitstream should be easy to modify if we know which bits they are :D | 12:06 |
| sorear | i'm going to keep pitching my "bitstreams with undefined symbols and relocations" idea as long as people keep asking for this | 12:06 |
| janrinze | sorear: would that be similar to having ip-blocks that don't need rebuilding? | 12:08 |
| sorear | there could be some overlap, but I can't comment more until I understand hierarchical PnR / floorplanning | 12:09 |
| janrinze | daveshah: is the floorplan a quad-tree? | 12:09 |
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| daveshah | the quadtree is used for handling mouse coordinates in the GUI | 12:11 |
| janrinze | daveshah: using a quadtree allows symmetric operations on cells like mirroring, rotation etc. to reduce wire length | 12:12 |
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| swetland | can't one invoke nextpnr and specify the random seed? presumably there should be some way to get identical outputs given suitably identical inputs -- since the PLL parameters don't affect placement, if everything else (including constraints, random seed, etc) is the same, shouldn't one be able to get the same layout? | 19:53 |
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| daveshah | Yes, you can specify the seed with --seed, it defaults to 1 | 20:08 |
| daveshah | It could be that your C++ library is randomising unordered_map ordering and we rely on that somewhere | 20:08 |
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| janrinze | daveshah: does up5k work okay with icepll generated pll? | 21:37 |
| janrinze | i get an error:ERROR: PLL 'mypll.uut' couldn't be placed anywhere, no suitable BEL found. Did you mean to use a PAD PLL ? | 21:39 |
| daveshah | You probably need to use a PAD PLL variant for your board | 21:41 |
| daveshah | This is dependent on which pin is used for clock output | 21:42 |
| janrinze | LOL.. yes that's what the error says | 21:42 |
| janrinze | but the 12 MHz is on a pad, right? | 21:42 |
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| janrinze | board is the up5k eval board | 21:42 |
| janrinze | lattice one, simple board. | 21:43 |
| janrinze | does the output have to be a pin too? | 21:43 |
| daveshah | No, the output can go to fabric or a global network | 21:44 |
| janrinze | okay, according to the docs pin 35 has 12MHz clock | 21:45 |
| janrinze | so i was assuming that can be used for pll input | 21:45 |
| daveshah | Yes, that is the dedicated PLL input pin so you have to use the _PAD not _CORE PLL variant | 21:46 |
| janrinze | aha! thanks! | 21:46 |
| janrinze | icepll by default generates a _CORE | 21:47 |
| janrinze | daveshah: i'll take a good look at your nes example to find out more things specific for the up5k. Already saw the spram there too. | 21:58 |
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| swetland | also, if you want to be able to use that 12M clock as well as the PLL generated clock you need to use SB_PLL40_2_PAD which provides the original clock as well as the generated clock | 22:49 |
| swetland | icepll probably should have options as to if the input is an IO or internal, what you're doing with the output, etc. the lattice clock wizard thing does, though their descriptions are a bit confusing. The docs for the SB_* blocks in http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201708.pdf are useful | 22:55 |
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