| *** tpb has joined #yosys | 00:00 | |
| *** seldridge0 has joined #yosys | 00:09 | |
| *** oter has joined #yosys | 00:54 | |
| *** seldridge0 has quit IRC | 00:58 | |
| *** wavedrom has joined #yosys | 01:32 | |
| *** oter has joined #yosys | 02:39 | |
| *** pie__ has joined #yosys | 02:43 | |
| *** oter has quit IRC | 02:49 | |
| *** pie___ has joined #yosys | 02:51 | |
| *** pie__ has quit IRC | 02:54 | |
| *** oter has joined #yosys | 03:00 | |
| *** pie___ has quit IRC | 03:31 | |
| *** rohitksingh has joined #yosys | 04:12 | |
| *** rohitksingh has quit IRC | 04:21 | |
| *** _whitelogger has quit IRC | 04:27 | |
| *** _whitelogger has joined #yosys | 04:29 | |
| *** rohitksingh has joined #yosys | 04:32 | |
| Kitlith | if you're using the synth_ice40 command of yosys, is there some way to pass -sv to do stuff with systemverilog? or is that automatically enabled or something? | 04:40 |
|---|---|---|
| *** oter has joined #yosys | 04:51 | |
| *** oter has quit IRC | 04:56 | |
| *** seldridge0 has joined #yosys | 05:04 | |
| *** seldridge0 has quit IRC | 06:20 | |
| *** dys has joined #yosys | 06:27 | |
| *** _whitelogger has quit IRC | 06:46 | |
| *** _whitelogger has joined #yosys | 06:53 | |
| *** wavedrom has quit IRC | 07:44 | |
| *** dys has quit IRC | 07:45 | |
| *** m4ssi has joined #yosys | 08:04 | |
| *** rohitksingh has quit IRC | 08:04 | |
| *** rohitksingh has joined #yosys | 08:05 | |
| *** rohitksingh_ has joined #yosys | 08:24 | |
| *** rohitksingh has quit IRC | 08:25 | |
| MoeIcenowy | Kltllth: I think -sv is proceed at Verilog loading stage | 08:39 |
| MoeIcenowy | not related to synthesis | 08:39 |
| *** kraiskil has joined #yosys | 09:16 | |
| *** rohitksingh_ has quit IRC | 09:19 | |
| *** rohitksingh has joined #yosys | 09:20 | |
| *** jcreus has joined #yosys | 09:54 | |
| ZipCPU | Kitlith: If you are using the Verific front end, "read -sv file.sv" will synthesize a SystemVerilog file | 11:51 |
| ZipCPU | Just like "read -vhdl file.vhd" will read and process a VHDL file. Both require the Verific front-end library, and so both require the commercial/licensed version of yosys | 11:53 |
| daveshah | read -sv will work without Verific too, that's the point of the new read command as opposed to the older Verific command | 12:16 |
| daveshah | Of course the subset of SV supported without Verific will be much smaller | 12:16 |
| *** _whitelogger has quit IRC | 12:54 | |
| *** _whitelogger has joined #yosys | 12:56 | |
| *** m_t has joined #yosys | 13:54 | |
| *** kraiskil has quit IRC | 14:37 | |
| *** pie___ has joined #yosys | 14:48 | |
| *** tmeissner has joined #yosys | 14:55 | |
| *** seldridge0 has joined #yosys | 14:58 | |
| *** dxld has quit IRC | 15:06 | |
| *** kraiskil has joined #yosys | 15:10 | |
| *** dxld has joined #yosys | 15:18 | |
| *** dxld has quit IRC | 15:24 | |
| *** dxld has joined #yosys | 15:27 | |
| *** X-Scale has quit IRC | 15:31 | |
| *** pie___ has quit IRC | 15:34 | |
| *** seldridge0 has quit IRC | 15:35 | |
| *** dxld has quit IRC | 15:35 | |
| *** tmeissner has quit IRC | 15:41 | |
| *** dxld has joined #yosys | 15:41 | |
| *** kristianpaul has joined #yosys | 15:50 | |
| *** tmeissner has joined #yosys | 16:08 | |
| *** m_t has quit IRC | 16:20 | |
| *** dys has joined #yosys | 16:25 | |
| *** kraiskil has quit IRC | 16:29 | |
| *** kraiskil has joined #yosys | 17:23 | |
| *** tmeissner has quit IRC | 17:32 | |
| *** pie__ has joined #yosys | 17:33 | |
| *** kraiskil has quit IRC | 17:43 | |
| *** jcreus has quit IRC | 17:50 | |
| *** rohitksingh has quit IRC | 17:54 | |
| *** rohitksingh has joined #yosys | 18:01 | |
| *** seldridge0 has joined #yosys | 18:05 | |
| *** jcreus has joined #yosys | 18:10 | |
| *** tmeissner has joined #yosys | 18:15 | |
| *** GuzTech has quit IRC | 18:29 | |
| *** pie__ has quit IRC | 18:31 | |
| *** pie__ has joined #yosys | 18:31 | |
| *** gruetzkopf has quit IRC | 18:40 | |
| *** gruetzkopf has joined #yosys | 18:41 | |
| *** tmeissner has quit IRC | 18:54 | |
| *** wavedrom has joined #yosys | 18:56 | |
| *** tmeissner has joined #yosys | 19:05 | |
| *** tmeissner has quit IRC | 19:11 | |
| *** mjoldfield has joined #yosys | 19:12 | |
| *** tmeissner has joined #yosys | 19:37 | |
| *** GuzTech has joined #yosys | 19:56 | |
| Kitlith | MoeIcenowy, i only asked because the commands i was seeing online never even seemed to use a read or read_verilog comand in addition to synth_ice40 | 20:03 |
| Kitlith | not using verific because "call for pricing" is an automatic "it's too expensive for me" as an individual | 20:06 |
| *** kraiskil has joined #yosys | 20:07 | |
| *** dys has quit IRC | 20:12 | |
| *** _whitelogger has quit IRC | 20:42 | |
| *** _whitelogger has joined #yosys | 20:44 | |
| *** pie__ has quit IRC | 20:47 | |
| *** tmeissner has quit IRC | 21:10 | |
| ZipCPU | Kitlith: You can both drive yosys from a command line and from a script. read_verilog or read are things you'll often see within the script, followed by one of the synth* commands | 21:11 |
| ZipCPU | You can also adjust parameters, macro defines, and more from with the script--things harder to do when calling the synth* command from the command line | 21:11 |
| *** pie__ has joined #yosys | 21:14 | |
| *** seldridge0 has quit IRC | 21:30 | |
| *** tmeissner has joined #yosys | 21:38 | |
| *** tmeissner has quit IRC | 21:58 | |
| *** rohitksingh has quit IRC | 21:59 | |
| *** dys` has joined #yosys | 22:47 | |
| *** kraiskil has quit IRC | 23:17 | |
| *** dys` has quit IRC | 23:22 | |
| *** pie__ has quit IRC | 23:42 | |
| *** jcreus has quit IRC | 23:46 | |
| *** pie__ has joined #yosys | 23:46 | |
| *** seldridge0 has joined #yosys | 23:57 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!