| *** tpb has joined #yosys | 00:00 | |
| *** jcreus has quit IRC | 00:16 | |
| *** vidbina has quit IRC | 00:17 | |
| *** m_w has quit IRC | 01:18 | |
| *** vidbina has joined #yosys | 01:38 | |
| *** _whitelogger has quit IRC | 02:15 | |
| *** _whitelogger has joined #yosys | 02:17 | |
| *** vidbina has quit IRC | 02:28 | |
| *** jevinskie has joined #yosys | 02:49 | |
| *** pie_ has joined #yosys | 03:11 | |
| *** pie__ has quit IRC | 03:12 | |
| *** _whitelogger has quit IRC | 04:15 | |
| *** _whitelogger has joined #yosys | 04:17 | |
| *** pie_ has quit IRC | 04:45 | |
| *** pie_ has joined #yosys | 04:57 | |
| *** jevinskie has quit IRC | 05:19 | |
| *** jevinskie has joined #yosys | 05:30 | |
| *** _whitelogger has quit IRC | 05:45 | |
| *** _whitelogger has joined #yosys | 05:48 | |
| *** pie_ has quit IRC | 05:53 | |
| *** _whitelogger has quit IRC | 06:46 | |
| *** hedgeberg has joined #yosys | 07:17 | |
| hedgeberg | Kitlith: freaking seriously? how many channels are you even in | 07:18 |
|---|---|---|
| hedgeberg | anyway, hiya, got a question re: systemverilog synthesis/PnR if anyone is in | 07:18 |
| hedgeberg | dm'ed clifford on twitter but I'm p sure he has bigger fish to fry, given 35c3 is a thing rn | 07:20 |
| hedgeberg | so, like, figured this was the best place to ask. Question is basically just: | 07:21 |
| hedgeberg | is enum currently supported? if so, what does it take to get yosys to play nice with it? | 07:22 |
| hedgeberg | I could swear I remember a twitter conversation during which clifford said it was supported, but now that I'm trying yosys for the first time I'm having 0 success | 07:22 |
| cr1901_modern | https://github.com/YosysHQ/yosys/issues/248 Looks like they aren't | 07:32 |
| tpb | Title: SystemVerilog enum types · Issue #248 · YosysHQ/yosys · GitHub (at github.com) | 07:32 |
| *** rohitksingh has joined #yosys | 07:33 | |
| *** _whitelogger has joined #yosys | 07:44 | |
| *** seldridge0 has quit IRC | 07:51 | |
| *** pie_ has joined #yosys | 07:59 | |
| hedgeberg | cr1901_modern fair enough. Any idea what it would take for someone with uh, all of 0 compiler experience to implement the enum token? | 08:17 |
| hedgeberg | also, while I'm at it, what's the status of supporting any of the Xilinx 7 series chips in nextpnr? | 08:17 |
| cr1901_modern | hedgeberg: My recommendation would be to read chapters 2 and 3 of Appel's Modern Compiler Implementation in C. It explains the theory behind lex and yacc so you (in principle) never have to impl it yourself. | 08:18 |
| hedgeberg | I remember hearing there had been some extensive RE of the bitstream format? is there anywhere I could go to see what has been done/needs to be done? | 08:18 |
| sorear | so https://github.com/YosysHQ/nextpnr/tree/xc7 was pushed yesterday but I'm not sure how much of a step towards the eventual long-term solution it is | 08:18 |
| tpb | Title: GitHub - YosysHQ/nextpnr at xc7 (at github.com) | 08:18 |
| sorear | https://symbiflow.github.io/#xray | 08:19 |
| tpb | Title: SymbiFlow (at symbiflow.github.io) | 08:19 |
| cr1901_modern | Or Dragon Book (which is what clifford read AIUI) | 08:19 |
| hedgeberg | o, that would make sense considering its 35c3 and therefore release time. | 08:19 |
| * cr1901_modern is currently reading the LR part of Chapter 3 | 08:20 | |
| hedgeberg | ok so I hate to be that guy, but... think I could figure it out by looking at how other tokens are handled in the compiler??? | 08:20 |
| sorear | the branch uses a third-party (and GPL3) tool "torc" to do some of the work | 08:20 |
| cr1901_modern | hedgeberg: YMMV. I'm a bit too stupid to figure it out w/o reading a book :P. | 08:20 |
| daveshah | Yes, this basically means it uses the official databases and ISE bitgen rather than XRay | 08:20 |
| hedgeberg | daveshah so, its not reversed from ISE/vivado? it instead uses xilinx's own data? | 08:21 |
| hedgeberg | fascinating, never heard of torc before. | 08:21 |
| daveshah | Yes, Torc is intended for use by universities, etc for research | 08:22 |
| daveshah | There's a more modern equivalent RapidWright for Vivado | 08:22 |
| hedgeberg | are they.. supported by xilinx?? i find that surprising | 08:22 |
| daveshah | It shouldn't be hard to move bitstream generation to use XRay FASM once XRay has IO support | 08:22 |
| *** wavedrom has quit IRC | 08:22 | |
| daveshah | I guess endorsed but not supported by Xilinx | 08:22 |
| hedgeberg | oooh, they have some virtex IV support. nice. maybe by the time I need to use my nice virtex IV board,it wont need to be with ISE. | 08:24 |
| *** jcreus has joined #yosys | 08:25 | |
| daveshah | With Torc you still have to use ISE for bitstream gen | 08:25 |
| hedgeberg | oh, bleh | 08:25 |
| hedgeberg | at least it removes the synthesizer/pnr from the loop | 08:25 |
| daveshah | Until someone (mwk hopefully) does bit docs for Virtex 4 at least | 08:25 |
| *** rohitksingh has quit IRC | 08:26 | |
| hedgeberg | mwk? | 08:26 |
| *** rohitksingh has joined #yosys | 08:26 | |
| daveshah | He's been looking at bitstream stuff for various Xilinx parts | 08:27 |
| hedgeberg | ngl part of me feels like its almost better to reverse than use other people's tools, but I also know thats probably not a good way of approaching this | 08:28 |
| hedgeberg | so, I guess this is something I've always been curious about, whats the level of difference between the bitstream and then PnR output? | 08:29 |
| daveshah | The PnR output is basically text describing functionality and routing | 08:30 |
| cr1901_modern | For the FOSS tools, the pnr output is ascii repr of bitstream | 08:30 |
| hedgeberg | I'm sure its clearly more complex than im assuming, but to my unfamiliar ape brain, I'd assume the pnr output and bitstream are 1-to-1 | 08:30 |
| daveshah | For xc7 and ecp5 the PnR output is higher level but still 1 to 1 | 08:30 |
| daveshah | For example we describe connectivity in terms of wire names | 08:31 |
| daveshah | This needs to be looked up to actual bits | 08:31 |
| hedgeberg | yeah, its like an assembler | 08:31 |
| * cr1901_modern wonders how much ice40 sales will take a nosedive once the series 7 bandwagon gets rolling | 08:31 | |
| hedgeberg | I think the ice40 chips will stick around for a while | 08:32 |
| hedgeberg | they had a real market before OSS stuff, and they'll have a real market afterwards too | 08:32 |
| sorear | if everyone in this chat buys a devboard that's how many ppb of lattice's volume? | 08:33 |
| daveshah | I think we will keep recommending ice40 for beginners stuff for a long time too | 08:34 |
| hedgeberg | anyway, I guess the reason im confused is that, if you can make a pnr output file where youve enabled some small set of routes/flipflops/gates/etc, and then run bitgen on it, it should be relatively simple to document how different pnr output elements correlate to bitstream? | 08:34 |
| daveshah | Yes, that's exactly what I did for ecp5 and similar to what clifford did for xray | 08:35 |
| sorear | I have no idea why we're following the gcc approach of having an assembler instead of the modern-compiler approach of generating binaries and having a disassembler for debugging | 08:35 |
| hedgeberg | and has noone done it for xc7 then? | 08:35 |
| daveshah | They have | 08:36 |
| sorear | the xc7 work doesn't include I/O cells yet, so it's difficult to demo | 08:36 |
| daveshah | It's just a bit rough around the edges and not the best place to start developing a PnR tool with right now | 08:36 |
| daveshah | And that | 08:36 |
| daveshah | You can work around the IO issue with partial reconfig, but when writing a PnR tool you want as few things as possible to debug | 08:37 |
| hedgeberg | sorear the use of an intermediate language etc honestly makes /more/ sense re: hdl to me than it does re: machine code | 08:37 |
| hedgeberg | yeah | 08:37 |
| daveshah | In particular Eddie was very familiar with Torc and XDL because of Verilog to bitstream in the past | 08:37 |
| daveshah | So it was a natural place to start | 08:38 |
| hedgeberg | like, in hdl you extract your state machines and your netlist, which is the perfect use for an intermediate representation imo | 08:38 |
| hedgeberg | also, what compilers come with decompilers? because that sounds amazing. I'd love to not have to use IDA anymore | 08:39 |
| daveshah | RTL ILs, the biggest thread in open source EDA, locked after 1000000 heated replies | 08:40 |
| hedgeberg | oh so I'm not the only one with A Strong Opinion(tm) on this subject | 08:40 |
| hedgeberg | ? | 08:40 |
| *** citypw has joined #yosys | 08:41 | |
| daveshah | https://github.com/SymbiFlow/ideas/issues/19 | 08:41 |
| tpb | Title: Lowlevel LLVM-like language as HDL middle layer · Issue #19 · SymbiFlow/ideas · GitHub (at github.com) | 08:41 |
| daveshah | Presented without comment | 08:42 |
| cr1901_modern | The OP is also a piece of work | 08:43 |
| hedgeberg | anyway, daveshah now that im a bit more up to date, ill prolly try to mess around with implementing enum into yosys over the next couple of days. assuming i somehow manage to make it work, i guess the main question then is where would it be best to throw in some work on xc7? | 08:43 |
| hedgeberg | working on reversing io cells? | 08:43 |
| daveshah | You could speak to digshadow about that? | 08:44 |
| hedgeberg | also yeah, cr1901_modern he seems like it tbh... | 08:44 |
| daveshah | He doesn't seem to be in this channel. Might be work asking in #symbiflow | 08:44 |
| cr1901_modern | hedgeberg: No I'm not bitter that the r*dare devs quote tweeted me, why do you ask? https://github.com/radare/r2hate/issues/7 | 08:45 |
| hedgeberg | anyway, why a language??? its a netlist + state machines... a low-level language seems like overkill? | 08:46 |
| hedgeberg | and, god, f*ck the r2 devs. | 08:46 |
| hedgeberg | I keep wanting to try r2, and every time I think of it, I remember how rude they are and continue to be. | 08:47 |
| cr1901_modern | There's no alternative, I refuse to use IDA, so I handroll my own dev env from open source "smart" tools | 08:48 |
| hedgeberg | also, cr1901_modern I /knew/ I recognized your name, just wasnt sure from where. | 08:48 |
| cr1901_modern | hedgeberg: Yea, I still owe you homework :) | 08:48 |
| daveshah | FWIW for the netlist nextpnr uses Yosys' own JSON format | 08:49 |
| hedgeberg | yeah, my place-of-work is an IDA shop, with a small group of binja users. Need to give binja a shot. | 08:49 |
| hedgeberg | neat | 08:49 |
| daveshah | This is quite a good format for netlists but not so good for the earlier stages of RTL | 08:49 |
| hedgeberg | cr1901_modern homework?? | 08:49 |
| cr1901_modern | daveshah: Also, RTLIL hasn't quite grown on me yet as pleasant to read, tbh | 08:50 |
| cr1901_modern | (as for earlier stages of RTL) | 08:50 |
| sorear | i don't interact often with people that make me wish github had site-wide moderation | 08:50 |
| hedgeberg | yeah, the steps before QM etc? tbh, I don't really know a good way off the top of my head to represent that step | 08:51 |
| daveshah | tbh I think RTLIL is intended more for internal use than as a real import or export target | 08:51 |
| cr1901_modern | Well, now that migen targets it (which I think is a decent idea), I have to read it | 08:51 |
| cr1901_modern | hedgeberg: https://twitter.com/hedgeberg/status/932636425631272962 | 08:51 |
| cr1901_modern | Btw, this is still kinda true... I'm bad at removing stuff from my todoist | 08:52 |
| hedgeberg | pffffft dude I had forgotten about this, that was so long ago | 08:52 |
| hedgeberg | fwiw, offer is still open | 08:52 |
| cr1901_modern | ty :3 | 08:52 |
| sorear | a Big Question which I'd like an answer to: what kind of IR is needed for a *friendly* mixed verilog/vhdl flow? | 08:52 |
| hedgeberg | but, yeah, i feel that :/ | 08:52 |
| sorear | source-to-source compilers are not the answer, unless you prefer f2c over g77 | 08:53 |
| cr1901_modern | sorear: Sadly enough, we talked about this in j-core a few months back | 08:53 |
| hedgeberg | sorear: idk tbh? maybe, like, some way to do large-block-netlisting? | 08:53 |
| cr1901_modern | the way to get j-core to work with yosys is probably to use nvc's IR, use the llvm backend to do vhdl elaboration, and then convert to verilog | 08:53 |
| sorear | do the EDA vendors have any emergent standard for how vhdl/verilog mixing works? | 08:54 |
| hedgeberg | PFFT | 08:54 |
| hedgeberg | absolutely not | 08:54 |
| cr1901_modern | I can instantiate simple VHDL IP in verilog code | 08:55 |
| cr1901_modern | that's the most I've ever done | 08:55 |
| hedgeberg | from what I can tell, xilinx/altera(rip)/cadence/etc refuse to standardize anything wherever possible | 08:55 |
| cr1901_modern | sorear: http://ix.io/1ngU (donnie_j is Jeff) | 08:56 |
| hedgeberg | so, I figure if anything they probably all have their own way of doing this and refuse to collaborate | 08:56 |
| sorear | I'm sorry, why wasn't this in #j-core ? | 08:56 |
| cr1901_modern | Because Jeff wasn't registered that night | 08:57 |
| cr1901_modern | and he was pressed for time | 08:57 |
| hedgeberg | what is j-core btw? | 08:57 |
| cr1901_modern | (#j-core only lets registered users speak) | 08:57 |
| hedgeberg | new to the OSS FPGA landscape, so a lot of this escapes me | 08:57 |
| cr1901_modern | hedgeberg: Remember superH? Dreamcast and Saturn and 32X? | 08:57 |
| cr1901_modern | it's a free version of that | 08:57 |
| sorear | cr1901_modern: how oten does this happen, any utility in my lurking #jcore? | 08:58 |
| hedgeberg | oooooooooooh | 08:58 |
| hedgeberg | gotcha | 08:58 |
| sorear | it's a … frustrating project to care about | 08:58 |
| cr1901_modern | sorear: In the past 2 years, that was the first time I've seen him on IRC | 08:58 |
| hedgeberg | at the risk of sounding ignorant, whats the benefit over riscv? | 08:58 |
| sorear | it's developed entirely behind closed doors by a team that speaks Japanese | 08:58 |
| cr1901_modern | (not the first time I've talked to him) | 08:58 |
| cr1901_modern | hedgeberg: Better insn density | 08:58 |
| cr1901_modern | it uses 16-bit insns | 08:58 |
| cr1901_modern | all the way thru. With all it's benefits and disadvantages | 08:59 |
| sorear | there is a version with a MMU. it is not public. the *programming documentation* for the MMU is not public. no, it's not the same as the Hitachi SH4 MMU | 08:59 |
| hedgeberg | ooh, neat, if not maybe a bit messy. | 08:59 |
| hedgeberg | sorear im so sorry for your loss | 08:59 |
| sorear | ? | 08:59 |
| sorear | it's not my loss | 08:59 |
| hedgeberg | sorry, im bad at jokes | 08:59 |
| cr1901_modern | sorear: There's nothing I can do about that. All I can do is be patient, because even if it's taking a while, I still want it to succeed | 08:59 |
| hedgeberg | im just quipping about the fact that it sounds like a horrible project to be invested in | 09:00 |
| cr1901_modern | The more free CPUs the merrier | 09:00 |
| cr1901_modern | That would explain why I haven't seen you chat in a while tho | 09:00 |
| sorear | the j-core project predates riscv, and they've focused on "make a small number of socs that are nice to use" over the broader-range platform questions | 09:01 |
| hedgeberg | oh | 09:01 |
| sorear | I'm there, I just don't really speak unless spoken to | 09:01 |
| cr1901_modern | or I'm asking a stupid question about PIC | 09:01 |
| hedgeberg | that sounds nice, tbh. I can appreciate that. | 09:01 |
| cr1901_modern | that also seems to get your attention | 09:01 |
| sorear | yes | 09:02 |
| hedgeberg | anyway, ill prolly give a stab at implementing enum over the next couple of days, so if im here a lot and asking a lot of annoying questions, thats why, and also im very sorry | 09:02 |
| cr1901_modern | don't be :P | 09:02 |
| sorear | i'm not a j-core expert but I know more than I should about ELF legalese | 09:02 |
| sorear | so I can answer those | 09:02 |
| cr1901_modern | sorear: In any case, I brought up this convo b/c: If j-core ever runs on yosys, using nvc is the way it's likely to happen | 09:03 |
| cr1901_modern | and that might be the only way to get verilog and vhdl to "play nice" | 09:03 |
| cr1901_modern | (in FOSS land) | 09:03 |
| sorear | sh is kinda similar to thumb1; the cost of the fixed 16-bit encoding is more instructions in common cases than arm32, because you can't use any register for any inptu and output | 09:03 |
| hedgeberg | that or make some completely new intermediate netlisting tool that can allow for abstract modules and link them together later? | 09:04 |
| hedgeberg | "link", i guess, since its very much not like linking in the software sense? | 09:05 |
| hedgeberg | idk if that sentence made sense at all i need coffee | 09:05 |
| sorear | cr1901_modern: see I would have assumed the hack answer was vhdl2vl | 09:05 |
| cr1901_modern | hedgeberg: Sorry it didn't make sense. But it's also 4am and I should be asleep | 09:05 |
| sorear | hedgeberg: the crux of my question above is "what is a module? discuss" | 09:06 |
| cr1901_modern | sorear: vhdl2vl isn't free I don't think? | 09:06 |
| sorear | https://github.com/ldoolitt/vhd2vl/blob/master/LICENSE ? | 09:06 |
| tpb | Title: vhd2vl/LICENSE at master · ldoolitt/vhd2vl · GitHub (at github.com) | 09:06 |
| cr1901_modern | Oh, I thought you were abbreviating vhdl2verilog | 09:06 |
| cr1901_modern | in any case, I know that tool now | 09:07 |
| cr1901_modern | j-core is too complex for it. nvc is the only free vhdl compiler that can handle j-core | 09:07 |
| cr1901_modern | and since I don't want to write a front end | 09:07 |
| cr1901_modern | I proposed bastardizing nvc to generate verilog | 09:07 |
| hedgeberg | i should go to bed too, fwiw, but i have a headache so going to sleep would actually suck more /with/ coffee than without | 09:07 |
| hedgeberg | no i got that backwards | 09:08 |
| cr1901_modern | (nvc's parser is 5000 lines. Handwritten.) | 09:08 |
| hedgeberg | i should stop trying to talk, ill be back tmrw probably o/ | 09:08 |
| cr1901_modern | set up a bouncer :)? | 09:08 |
| cr1901_modern | or just keep your client on (like I do lol) | 09:09 |
| hedgeberg | meh | 09:09 |
| hedgeberg | yeah, thats the plan, i was jsut saying bye for good manners. im not logging off | 09:09 |
| hedgeberg | one day when i finish my new home server architecture, ill resume running a znc instance | 09:09 |
| hedgeberg | until then, meh, not on irc enough to bother | 09:09 |
| sorear | nvc versus ghdl? the j-core tarball includes ghdl makefile bits | 09:14 |
| cr1901_modern | I forgot the deal w/ ghdl | 09:15 |
| daveshah | There is ghdlsynth, but it only supports a small subset of functionality (less than vhdl2vl on my testing) | 09:18 |
| cr1901_modern | tbqh, it's probably easier to write a "competing" impl in verilog or migen and feed it to yosys lmao | 09:19 |
| cr1901_modern | maybe not the MMU or multicore version | 09:19 |
| cr1901_modern | but I don't need either of those for my use cases (use sh2 w/ litex) | 09:19 |
| * cr1901_modern should prob go to bed for real this time and _not_ watch more anime | 09:23 | |
| sorear | (not a reply) the only HDLs I have much knowledge of relevant to implementation are systemverilog and bluespec | 09:23 |
| sorear | i'd like to spend time studying (n)migen, vhdl, clash, kami, etc | 09:24 |
| cr1901_modern | well verilog is just boneless systemveri- | 09:24 |
| cr1901_modern | /me is smacked | 09:24 |
| sorear | IMO verilog is "what people called systemverilog prior to 2005" | 09:24 |
| cr1901_modern | systemverilog is "super"-verilog | 09:25 |
| sorear | this doesn't seem to be a case like C and C++ where WG11 continues to exist and continues to make new standards that are incompatible in new and exciting ways with what WG14 did | 09:25 |
| sorear | *WG14 and WG21 | 09:25 |
| cr1901_modern | C seems to be... not updated that often? | 09:26 |
| cr1901_modern | I think there's a C20, but it's meh | 09:26 |
| cr1901_modern | And as for bluespec- not interested in Haskell, sorry | 09:26 |
| sorear | there was an 11 year gap between (s)v specs so whatever | 09:26 |
| cr1901_modern | I just don't grok it and I don't think I ever will | 09:27 |
| sorear | it hasn't used haskell syntax in a decade | 09:27 |
| cr1901_modern | I just am going by the wiki article :) | 09:27 |
| *** rohitksingh has quit IRC | 09:28 | |
| sorear | although bluespec's elaboration-time semantics are basically identical to haskell 98 + MultiParameterTypeClasses + FunctionalDependencies | 09:29 |
| * cr1901_modern knows some of those words | 09:29 | |
| cr1901_modern | I do fully admit that it isn't an accident formal flows like SMTv2 look like pure functional languages | 09:30 |
| *** rohitksingh has joined #yosys | 09:35 | |
| *** hedgeberg has quit IRC | 09:37 | |
| sorear | in which I notice that ghdl is written in Ada | 09:41 |
| sorear | _fitting_ but annoying | 09:41 |
| *** citypw has quit IRC | 10:12 | |
| *** hedgeberg has joined #yosys | 10:13 | |
| *** rohitksingh has quit IRC | 10:24 | |
| *** rohitksingh has joined #yosys | 10:34 | |
| *** m_t has joined #yosys | 10:38 | |
| *** maikmerten has joined #yosys | 10:47 | |
| maikmerten | just finished watching the wonderful SymbiFlow talk from 35C3. Great presentation! | 10:47 |
| maikmerten | just wondering if the "hostile towards Open Source" regarding Lattice is a new (active) development or the usual (?) passive "no specs for you" | 10:49 |
| daveshah | Lattice are *not* hostile towards open source | 10:50 |
| daveshah | idek why that was mentioned | 10:50 |
| maikmerten | ah, great | 10:50 |
| maikmerten | okay, that confused me a bit | 10:50 |
| daveshah | yes, particularly if you've been following @ico_TC recently.. | 10:50 |
| maikmerten | well, I've watched the risc-v softcpu contest, with Lattice actually spreading boards and the yosys toolchain *not* being discouraged | 10:52 |
| sorear | at the end mithro talked about some fpga vendors being hostile/neutral/supportive, but didn't name names for any category | 10:52 |
| daveshah | even at Xilinx there are certainly individuals who are very supportive of open source (hence rapidwright) | 10:54 |
| sorear | Silego/Dialog gave azonenberg bitstream documentation for the GreenPAK, which he used for yosys support a few years ago (and a separate tool "gp4par") | 10:54 |
| sorear | in the 90s there was a company that did gate-array ASICs layout-compatible with some Altera part, and their flow involved using Quartus to synthesize and pnr a customer design, then $company would convert the bitstream into metal masks | 10:56 |
| sorear | Altera sued them on the grounds that they were inciting customers to violate Altera's EULA (which only permits use to program Altera devices) | 10:57 |
| sorear | it's unclear how relevant this is to what we do | 10:57 |
| maikmerten | heh, IIRC Altera also happened to offer mask-programmed parts based on some of their FPGAs | 10:57 |
| maikmerten | (they don't anymore) | 10:57 |
| nats` | if it's like xilinx it's not mask programlmed | 10:59 |
| nats` | they just sell you a fpga tested with your design | 10:59 |
| nats` | and it's cheaper because many function can be defective but you don't care | 10:59 |
| nats` | (but obviously you can't use the fpga with an other design or only at your own risk) | 10:59 |
| daveshah | Lattice had something like this at one point too (FreedomChip) | 11:01 |
| daveshah | I understand this also involves some kind of soft scan chain insertion during synthesis | 11:01 |
| sorear | Microchip/Microsemi didn't seem especially enthusiastic about icestorm in 2016 but I have no idea what the current status is | 11:03 |
| *** rohitksingh has quit IRC | 11:33 | |
| *** rohitksingh has joined #yosys | 11:45 | |
| MoeIcenowy | sorear: the AGM FPGA chips I recently researching recommends to use Quartus to synthesis... | 11:52 |
| MoeIcenowy | (although the toolchain also supports to use yosys to synthesis | 11:53 |
| *** pie_ has quit IRC | 11:54 | |
| sorear | I saw that on twitter (and now I see you have the same nick as the person who posted there) | 11:55 |
| *** vidbina has joined #yosys | 11:57 | |
| sorear | from the nvc blog: | 12:00 |
| sorear | > But I have a question: why did you choose C instead of C++ ? | 12:00 |
| sorear | > Two reasons I suppose: [...]; the second is that I find it much easier to “get things done” in C – in C++ I waste time agonising which of N possible ways I should choose to implement something: in C I just write the code ;-). | 12:01 |
| sorear | WAY TOO FAMILIAR | 12:01 |
| *** vidbina has quit IRC | 12:06 | |
| *** vidbina has joined #yosys | 12:12 | |
| *** MoeIcenowy has quit IRC | 12:39 | |
| *** MoeIcenowy has joined #yosys | 12:40 | |
| sorear | ideally, we would have one high quality open source verilog + vhdl frontend which could be used for linting, event simulation, wire-level simulation, synthesis, and formal verification | 12:56 |
| sorear | what we have: (a) a verilog-only frontend which deliberately cuts corners (IIRC) with error messages, can be used for synthesis and formal | 12:57 |
| sorear | (b) verilator's frontend which does wire-level sim and linting (c) iverilog's frontend which does event simulation and linting (d) ghdl (linting and events) (e) nvc (linting and events) | 12:58 |
| *** maikmerten has quit IRC | 13:09 | |
| *** dys has quit IRC | 13:46 | |
| *** vidbina has quit IRC | 13:48 | |
| *** vidbina has joined #yosys | 14:06 | |
| *** citypw has joined #yosys | 14:29 | |
| *** dys has joined #yosys | 14:55 | |
| *** AlexDaniel has quit IRC | 15:00 | |
| *** cdleary has joined #yosys | 15:09 | |
| cdleary | daveshah: thanks for doing the talk on project trellis at ORConf, are things at a point where a versa dev board (with the PCIex1) is a reasonable thing to get for yosys-flow-based development? (lmk if there somewhere I should have checked instead of asking in chat? :-) tia! | 15:15 |
| *** m_t has quit IRC | 15:21 | |
| daveshah | As far as readily available boards go, I'd recommend the Versa-5G or the LFE5UM5G-85F-EVN | 15:21 |
| daveshah | There are examples for both of these inside Trellis | 15:21 |
| *** jcreus has quit IRC | 15:24 | |
| *** jcreus has joined #yosys | 15:25 | |
| cdleary | daveshah: cool, I see that now! inferring from one of these config files that it's programmed via FTDI interface like on the ice40 boards, do those expose the UART to the FPGA on those boards as well? I can't find a datasheet that shows the uart pins ATM (Ibut I'd assume so? | 15:46 |
| MoeIcenowy | daveshah: by the way is ECP5 programmed via JTAG or SPI? | 15:46 |
| daveshah | cdleary: yes, they do. The Versa connects them by default, you need to solder some 0R resistors to get it on the EVN board | 15:47 |
| daveshah | MoeIcenowy: it can do either, but most boards use JTAG | 15:47 |
| MoeIcenowy | ah okay | 15:47 |
| MoeIcenowy | to be honest that iCE40 can only programming via SPI seems strange ;-) | 15:48 |
| daveshah | I think the iCE40 was supposed to have JTAG, some of the early docs mention it | 15:48 |
| MoeIcenowy | and to be honest I consider the FT232H programmer still too expensive ;-) | 15:49 |
| daveshah | more expensive than the FPGA... | 15:49 |
| daveshah | you can use an STM32 too | 15:49 |
| daveshah | https://github.com/mystorm-org/BlackIce-II | 15:50 |
| tpb | Title: GitHub - mystorm-org/BlackIce-II: Software, Firmware and documentation for the myStorm BlackIce-II board (at github.com) | 15:50 |
| MoeIcenowy | I think it's possible to use any USB2SPI, but iceprog only supports FT232H... | 15:50 |
| daveshah | yeah | 15:50 |
| cdleary | daveshah: I was trying to see how your fuzzer did its I/O as well to observe changed bits without perturbing the dut, trawling the code is fun, but any key pointers/hints? :-) | 15:50 |
| MoeIcenowy | to be honest the cheapest chip I have seen on a USB2SPI board is WCH CH551G/CH552G | 15:50 |
| daveshah | cdleary: The fuzzing is all based on creating a large number of bitstreams, mostly using the 'ncl' post-place-and-route-design format, with Diamond and looking for the changes in the bitstream | 15:51 |
| MoeIcenowy | daveshah: by the way will the fuzzing be possible without tile -> bitstream position info? | 15:52 |
| daveshah | Yes | 15:52 |
| MoeIcenowy | The way to generate tilegrid in prjtrellis gives out the tile position | 15:52 |
| daveshah | if you can manually create, e.g. a LUT, in every tile, you should be able to work out the tile offsets more or less | 15:52 |
| MoeIcenowy | but in prjtang TD do not give out this info | 15:53 |
| cdleary | daveshah: oh I see, no need to talk to the device at all e.g. to confirm connectivity? I was thinking of it kind of like a manufacturing test where you see if bits really push from point a to point b at the end | 15:53 |
| daveshah | no, no hardware is involved in fuzzing | 15:53 |
| daveshah | connectivity uses a mixture of the tcl api and bitstream diffing | 15:54 |
| cdleary | daveshah: gotcha, makes sense now | 15:54 |
| MoeIcenowy | by the way mmicko found how to decrypt the TD database, but he doesn't dare to use data in it... | 15:55 |
| sorear | there is 1 NC pin on (one? several?) of the ice40 packages and there has been speculation here that it's /TRESET | 16:08 |
| sorear | what's TD? | 16:08 |
| MoeIcenowy | sorear: the tool of Anlogic FPGAs | 16:09 |
| MoeIcenowy | Anlogic is a Chinese FPGA company | 16:09 |
| *** xerpi has joined #yosys | 16:39 | |
| *** vidbina has quit IRC | 16:55 | |
| *** kraiskil has joined #yosys | 16:58 | |
| *** citypw has quit IRC | 16:59 | |
| *** vidbina has joined #yosys | 17:00 | |
| *** seldridge0 has joined #yosys | 17:01 | |
| *** kraiskil has quit IRC | 17:09 | |
| *** vidbina has quit IRC | 17:13 | |
| *** mjoldfield has quit IRC | 17:13 | |
| *** mjoldfield has joined #yosys | 17:14 | |
| *** kraiskil has joined #yosys | 17:16 | |
| *** tpw_rules has joined #yosys | 17:33 | |
| tpw_rules | hey all. i just saw mithro's talk about symbiyosis and am interested in working with that project. i'm more familiar with altera devices so maybe i could work on them somehow? is he around here much? | 17:34 |
| daveshah | mithro is here, but for that kind of stuff you might be better off asking on #symbiflow | 17:35 |
| tpw_rules | oh ok, i didn't see that channel in the talk. thank you | 17:35 |
| sorear | have you talked to rqou yet? | 17:35 |
| *** lutsabound has joined #yosys | 17:35 | |
| tpw_rules | no | 17:35 |
| sorear | (did some work on MAX V) | 17:35 |
| sorear | (is at 35c3 rn) | 17:36 |
| rqou | uh, hi | 17:36 |
| rqou | if you're at 35c3, you can call me at 8838 | 17:36 |
| tpw_rules | no, i'm not | 17:36 |
| tpw_rules | my only interaction so far has been twitter rumors and the talks | 17:38 |
| tpw_rules | i have not so much intelligence but lots of computers and time | 17:39 |
| qu1j0t3 | haha, i have little intelligence or time, but plenty of computers | 17:40 |
| tpw_rules | well i'll probably come back when the c3 business has died down a little. i would be interested in talking to rqou later | 17:44 |
| *** tpw_rules has left #yosys | 17:51 | |
| *** maikmerten has joined #yosys | 18:01 | |
| maikmerten | MoeIcenowy, these AGM chips look interesting | 18:03 |
| maikmerten | a bit confused how they apparently (?) can recommend Quartus | 18:03 |
| sorear | only for synthesis right? | 18:04 |
| maikmerten | are those hardware clones, or do they "only" borrow certain parts of synthesis and transform this to whatever they actually implemented? | 18:04 |
| daveshah | As far as I know only synthesis | 18:04 |
| daveshah | They aren't bitstream compatible or anything | 18:05 |
| maikmerten | ah, good for them, I guess | 18:05 |
| maikmerten | (albeit perhaps still not good for their users, Quartus EULA and whatnot - but then again if they also have yosys...) | 18:06 |
| daveshah | Altera have sued in the past, too | 18:08 |
| daveshah | https://revisionlegal.com/revision-legal/how-bad-can-it-be-infringement-penalties-under-the-scpa/ | 18:08 |
| tpb | Title: How Bad Can It Be? Penalties Under the SCPA | Revision Legal (at revisionlegal.com) | 18:08 |
| sorear | let's get rid of any qor difference ;) | 18:08 |
| daveshah | :) | 18:08 |
| *** vidbina has joined #yosys | 18:15 | |
| sorear | cr1901_modern: what are your CPI and resource utilization targets. actually what would you be doing with sh+litex | 18:17 |
| cr1901_modern | CPI of 1, fit very comfortably on up5k. Could serve as a micropython target for fomu/tinyfpga | 18:24 |
| sorear | micropython already supports or1k and riscv I think? | 18:26 |
| sorear | average CPI 1 is … beyond what j-core can do I think | 18:28 |
| cr1901_modern | or1k is never going to fit onto up5k | 18:29 |
| maikmerten | I think in the risc-v softcpu contest there were compact ~1 CPI designs | 18:29 |
| cr1901_modern | well mor1k anyway | 18:29 |
| *** cdleary has quit IRC | 18:29 | |
| cr1901_modern | sorear: By CPI of 1, I simply mean "classic RISC pipeline" | 18:30 |
| cr1901_modern | it's the theoretical limit, I'm guessing the actual CPI in practice will be 0.7-0.8? | 18:30 |
| cr1901_modern | err, whoops | 18:30 |
| maikmerten | winner: https://github.com/SpinalHDL/VexRiscvSoftcoreContest2018 | 18:30 |
| tpb | Title: GitHub - SpinalHDL/VexRiscvSoftcoreContest2018 (at github.com) | 18:30 |
| maikmerten | (classical RISC pipeline) | 18:30 |
| cr1901_modern | 1/0.7 to 1/0.8 | 18:31 |
| sorear | not counting cache misses, probably around there, maybe 1/0.9 | 18:31 |
| sorear | I don't have a great feel for the fraction of fun instructions like postincremnt | 18:31 |
| sorear | this spreadsheet is suprisingly comprehensible | 18:33 |
| sorear | concerned by the PC = INC / HOLD column though | 18:34 |
| cr1901_modern | vexriscv currently does run on litex, but at present there's issues with wishbone conversion layer. Minimum 1193 logic cells is nice though (compared to ~1500 for anything litex uses for up5k right now). | 18:35 |
| sorear | *puts 2 and 2 together* I am skeptical j-core will fit | 18:39 |
| sorear | their target board is a 9K LUT6 s6, and it probably hasn't come into contact with ice40's "no distributed RAM" quirk | 18:40 |
| cr1901_modern | Well, I can still humor a competing impl :P | 18:53 |
| *** maikmerten has quit IRC | 18:57 | |
| *** kraiskil has quit IRC | 19:10 | |
| *** mjoldfield has quit IRC | 19:21 | |
| *** mjoldfield has joined #yosys | 19:22 | |
| *** freemint has joined #yosys | 19:42 | |
| sorear | o/ | 19:43 |
| sorear | (see topic if you're unclear on what this is) | 19:43 |
| *** vidbina has quit IRC | 19:45 | |
| *** vidbina has joined #yosys | 19:55 | |
| *** vidbina has quit IRC | 20:11 | |
| *** rohitksingh has quit IRC | 20:14 | |
| *** vidbina has joined #yosys | 20:37 | |
| *** xerpi has quit IRC | 20:45 | |
| *** arnd has joined #yosys | 20:53 | |
| *** xerpi has joined #yosys | 21:00 | |
| *** vidbina has quit IRC | 21:05 | |
| *** vidbina has joined #yosys | 21:17 | |
| *** kraiskil has joined #yosys | 21:52 | |
| *** kraiskil_ has joined #yosys | 21:59 | |
| *** kraiskil has quit IRC | 22:01 | |
| *** mjacob has joined #yosys | 22:03 | |
| *** seldridge0 has quit IRC | 22:07 | |
| *** kraiskil__ has joined #yosys | 22:26 | |
| *** kraiskil_ has quit IRC | 22:29 | |
| *** kraiskil__ has quit IRC | 22:35 | |
| *** wavedrom has joined #yosys | 22:36 | |
| ZipCPU | sorear: What's wrong with a S6/LX9? It can be done if you use your resources wisely. I managed to put a multi-tasking O/S on one of those even. | 22:37 |
| *** kraiskil__ has joined #yosys | 22:37 | |
| sorear | ZipCPU: nothing. cr1901_modern wants to take a design that's proven on xc6slx9 and run it on ice40up5k, but the latter is about a third the size | 22:44 |
| ZipCPU | Ooohhh .... okay. That makes more sense of the conversation | 22:44 |
| sorear | (i'm assuming s6 is also a LUT6 family and applying the 1.4x fudge factor) | 22:45 |
| cr1901_modern | sorear: I'm pretty sure that's the whole soc though, not just the CPU core | 22:45 |
| ZipCPU | One of the tricks to getting the S6SoC I built running was being *VERY* judicious with how the peripherals were built .. | 22:45 |
| *** xerpi has quit IRC | 23:01 | |
| *** xerpi has joined #yosys | 23:01 | |
| *** pie_ has joined #yosys | 23:54 | |
| *** pie_ has quit IRC | 23:55 | |
| *** pie_ has joined #yosys | 23:55 | |
| *** pie_ has quit IRC | 23:59 | |
| *** pie_ has joined #yosys | 23:59 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!