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| mithro | ZipCPU: Do you know what "ERROR: Failed to import cell $techmap\gold.$procdff$3319 (type $adff) to SAT database." mean - do I need to do something like adff to dff or import https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v ? | 01:42 |
|---|---|---|
| tpb | Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com) | 01:42 |
| ZipCPU | Hi, mithro | 01:43 |
| ZipCPU | I hate to ask, but .... what are you trying to accomplish? I normally only get the adff bug when doing formal methods | 01:43 |
| ZipCPU | Regular synthesis? | 01:44 |
| mithro | Trying to prove equivalence of a bitstream to initial verilog using a magic script that daveshah gave me :-P | 01:44 |
| ZipCPU | Are you using symbiyosys, or just yosys? | 01:45 |
| ZipCPU | yosys-smtbmc that is | 01:45 |
| ZipCPU | well ... I guess I mean yosys/yosys-smtbmc .... 'cause the answer is different depending on which you are using. | 01:45 |
| mithro | symbiflow-arch-defs/env/conda/bin/yosys -p "rename top gate; read_verilog symbiflow-arch-defs/ice40/tests/ffpack/example.v; rename top gold; hierarchy; proc; miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter; sat -dump_vcd symbiflow-arch-defs/ice40/tests/ffpack//build-ice40-top-routing-virt-hx1k/out.vcd -verify-no-timeout -timeout 20 -seq 1000 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs | 01:46 |
| mithro | miter" symbiflow-arch-defs/env/conda/share/yosys/ice40/cells_sim.v symbiflow-arch-defs/ice40/tests/ffpack//build-ice40-top-routing-virt-hx1k/example_bit.v | 01:46 |
| ZipCPU | Ok: add clk2fflogic to your flow. | 01:46 |
| mithro | ZipCPU: after the proc? | 01:47 |
| ZipCPU | Yes. | 01:48 |
| mithro | ZipCPU: What does the clk2fflogic do? | 01:48 |
| ZipCPU | The problem is ... without the clk2fflogic, yosys may or may not handle the asynchronous reset's properly. | 01:48 |
| ZipCPU | clk2fflogic separates the clock within the design from the SMT timestep. The clock becomes a separate input that may need to be assumed to be toggling. | 01:49 |
| mithro | Okay, this definitely has an async reset | 01:49 |
| ZipCPU | It helps with async resets. | 01:49 |
| ZipCPU | That said, Clifford recently fixed SymbiYosys up for me so it didn't need clk2fflogic in order to implement async resets. | 01:49 |
| ZipCPU | Not really sure what he did different. (That was this week or last.) | 01:50 |
| mithro | https://www.irccloud.com/pastebin/B6jfU8Vn/ | 01:50 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 01:50 |
| ZipCPU | If you just run symbiyosys, you might see a different (perhaps better) yosys/command/approach ... | 01:50 |
| * ZipCPU pulls up a browser ... | 01:50 | |
| ZipCPU | timeout? | 01:51 |
| mithro | I should expand `-timeout` I assume? | 01:52 |
| ZipCPU | Not sure. | 01:53 |
| ZipCPU | I've actually never used the equivalence checking myself. | 01:53 |
| mithro | Is it likely something with 1233925 variables and 3262769 clauses likely to finish? | 01:53 |
| ZipCPU | I've never seen that statement before. I don't know. | 01:54 |
| mithro | Well - it does seem to have finished.... | 01:55 |
| mithro | If I recall correctly, any time the cmp_ values is not 1 is a case where the circuits differ... | 01:56 |
| mithro | I actually think I can do something simpler - just run both verilog files with the same test bench and then compare the output.... | 01:59 |
| mithro | https://usercontent.irccloud-cdn.com/file/5g0SNHRC/image.png | 02:01 |
| mithro | Think that shows the two circuits aren't logic equiv but not really sure... | 02:06 |
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| ZipCPU | Another interesting test: Create a top level feeding both circuits the same inputs, and asserting that the outputs are the same. | 02:20 |
| ZipCPU | It's not quite as good as equivalence checking, but ... it's more along the lines of the parts of yosys I've personally used. | 02:20 |
| ZipCPU | Only problem is .... if you can't get an assertion failure in the first N clocks, the conclusion you are looking for will be undetermined. | 02:20 |
| mithro | ZipCPU: This is the bug we have been thinking about -> https://github.com/SymbiFlow/symbiflow-arch-defs/issues/144 | 02:22 |
| tpb | Title: Create an ice40 test for the packing of different types of flip flops together · Issue #144 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 02:22 |
| * ZipCPU takes a peek | 02:23 | |
| ZipCPU | How many LUT's are in your comparison? 1? 8? Many more? | 02:25 |
| mithro | ZipCPU: Hrm? In this test we don't really care about the LUTs here... Just having enough flip flops to test packing is working... | 02:30 |
| ZipCPU | Ahh, sorry ... wrong term ... thanks for the correction. | 02:30 |
| mithro | ZipCPU: The packer uses connectivity to pack together -- so, interested in different groupings and making sure that the packing is doing the right thing | 02:38 |
| mithro | Some FF types can be packed together into a tile, some can't, etc | 02:39 |
| mithro | ZipCPU: But too lazy to write all the tests by hand :-P | 02:42 |
| ZipCPU | :D | 02:42 |
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| mithro | So it seems that yosys can't import it's own simlib.v? ERROR: System task `$stop' outside initial block is unsupported at symbiflow-arch-defs/env/conda/share/yosys/simlib.v:1282. | 02:58 |
| mithro | Seems like I need something like -DSIMLIB_NOCHECKS ? | 02:58 |
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| mithro | ZipCPU: Have you used yosys's "sim" command? | 03:34 |
| ZipCPU | No, I haven't. I love what I can do with Verilator way too much. | 03:41 |
| mithro | ZipCPU: Any chance you'd be interested in adding a verilator version of these commands -> https://github.com/mithro/symbiflow-arch-defs/blob/ffpack_tb_sr/make/tests.mk#L190-L220 and https://github.com/mithro/symbiflow-arch-defs/blob/ffpack_tb_sr/make/tests.mk#L358-L378 ? | 03:49 |
| tpb | Title: symbiflow-arch-defs/tests.mk at ffpack_tb_sr · mithro/symbiflow-arch-defs · GitHub (at github.com) | 03:49 |
| ZipCPU | Let me take a peek in the morning, it's getting quite late here. | 03:50 |
| mithro | ZipCPU: No hurry, the iverilog version works okay | 03:54 |
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| ZipCPU | mithro: Looking at the iverilog Makefile commands you cited last night. I'm curious ... how long does iverilog take to do these simulations for you? | 12:21 |
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| maikmerten | mattvenn, some more work on the HX8K breakout board SRAM/PMOD wing - now with buttons ;-) | 15:29 |
| maikmerten | https://pasteboard.co/HwgaQj8.png | 15:29 |
| tpb | Title: Pasteboard Uploaded Image (at pasteboard.co) | 15:29 |
| mattvenn | looks good! | 15:32 |
| mattvenn | I take it there aren't enough pins to get a 8pin pmod on the bottom? | 15:32 |
| mattvenn | also - liking the silkscreen on the pmods - nice work! | 15:32 |
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| maikmerten | mattvenn, sorry, not enough pins available for another 8-pin :-( | 15:33 |
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| maikmerten | hmm... having the decoupling capacitor for the SRAM that far away somewhat defeats the purpose | 15:35 |
| * maikmerten tries to remedy this | 15:35 | |
| mattvenn | not a big deal | 15:36 |
| mattvenn | I can't see the back, but assuming you're using another 8 wires for the sram on the back | 15:36 |
| mattvenn | if you don't have 8, then use them all up with buttons and leds! | 15:37 |
| mattvenn | sorry I meant 4 | 15:37 |
| mattvenn | as you've already got 4 | 15:37 |
| mattvenn | keep me posted. I've got to go early today - will check back tomorrow | 15:38 |
| maikmerten | yeah, I'm routing some SRAM signals on the back side - which is why there's a row of vias on the south-east of the SRAM chip | 15:40 |
| maikmerten | (the resistor network for those is also on the back) | 15:41 |
| maikmerten | *networks | 15:41 |
| maikmerten | somewhat better decoupling: https://pasteboard.co/HwgiV0G.png | 15:47 |
| tpb | Title: Pasteboard Uploaded Image (at pasteboard.co) | 15:47 |
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| mithro | ZipCPU: A couple of seconds at the moment | 16:59 |
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| ZipCPU | mithro: Then it doesn't sound like you need a redesign at all, right? | 18:38 |
| mithro | ZipCPU: Nope - don't need a redesign -- just want to add support for verilator as an alternative to iverilog -- probably be useful for faster simulation when we have bigger designs.... | 18:38 |
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| mithro | ZipCPU: IE Full SoCs | 18:48 |
| ZipCPU | Heheh ... Full "post-synthesis" SoC's? That'd be ... a fun challenge. I know I use Verilator on full SoC's often enough myself, just never post synthesis. | 18:49 |
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| mithro | ZipCPU: sorry, post pnr - not post synthesis | 22:00 |
| ZipCPU | From a Verilator standpoint, there wouldn't be any difference. | 22:01 |
| ZipCPU | In both examples, you lose one of the great benefits of Verilator--being able to do word ops. The other great benefit of Verilator is being able to operate on 0 and 1, rather than 0, 1, z, and x. | 22:02 |
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