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| mattvenn | ZipCPU: what's a word op? | 08:15 |
|---|---|---|
| mattvenn | operating on a whole bus at once? | 08:16 |
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| ZipCPU | Yes. For example, reg [15:0] a; always @(posedge i_clk) if (reset) a <= 0; else a <= a+ 1; | 10:17 |
| ZipCPU | The other thing I like about Verilator is the ease of mixing it with C++. But that's another story. | 10:19 |
| ZipCPU | mattvenn: Hopefully that answers your question. | 10:19 |
| mattvenn | thanks | 10:31 |
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| promach_ | ZipCPU: is it possible that yosys could interpret a negative edge as posedge ? | 14:47 |
| ZipCPU | Not likely. | 14:48 |
| promach_ | Can I show you the trace which illustrates the opposite ? | 14:50 |
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| ZipCPU | Sure | 14:53 |
| ZipCPU | But make sure you explain it as well. | 14:53 |
| promach_ | https://i.imgur.com/VTw7bZu.png | 15:05 |
| promach_ | ZipCPU: cnt is not 0 for smt_step >= 149 | 15:05 |
| promach_ | assertion at line 299 | 15:06 |
| promach_ | I am referring this with reference to rx_clk | 15:06 |
| ZipCPU | What sets cnt? | 15:06 |
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| ZipCPU | Oh, and is your repo up to date? | 15:07 |
| promach_ | ZipCPU: yes | 15:07 |
| promach_ | https://github.com/promach/UART/blob/development/rtl/test_UART.v#L299 | 15:08 |
| tpb | Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com) | 15:08 |
| ZipCPU | Lol | 15:09 |
| ZipCPU | You are setting cnt on the positive edge of tx_clk | 15:09 |
| ZipCPU | So, ... it changes on the positive edge of the tx_clk | 15:09 |
| promach_ | I would say that this is not a problem at all | 15:09 |
| ZipCPU | You are checking cnt on the positive edge of rx_clk. tx_clk and rx_clk are out of phase by 180 degrees, hence the appearance of a negative edge issue. | 15:10 |
| ZipCPU | Well, I suppose it is a problem .... just not yosys' problem | 15:10 |
| promach_ | and yosys seems to interpret posedge rx_clk differently | 15:10 |
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| ZipCPU | Differently? | 15:13 |
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| promach_ | yes | 15:14 |
| promach_ | see smt_step=148 | 15:15 |
| promach_ | yosys should have executed the assertion at step 148 instead of 149 | 15:15 |
| ZipCPU | You mean the assertion that eventually failed, the one on line 299? | 15:18 |
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| promach_ | YES | 15:19 |
| ZipCPU | How are you running this? Your makefile only runs 10 steps | 15:21 |
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| ZipCPU | I just tried running your code, and it passed with an induction length of 90. | 15:25 |
| ZipCPU | I must be looking at the wrong branch | 15:25 |
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| promach_ | sby -f UART.sby | 15:38 |
| promach_ | ZipCPU | 15:38 |
| promach_ | use development branch | 15:43 |
| promach_ | passed with an induction length of 90 ??? | 15:43 |
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| ZipCPU | Ok, so .... the rx_clk rises and an assertion depending upon the rise of rx_clk fails. Not sure the issue here. | 15:48 |
| promach_ | ZipCPU: are you getting assertion failure at line 299 ? | 15:49 |
| promach_ | I mean the trace | 15:49 |
| promach_ | did you have your own trace now ? | 15:50 |
| ZipCPU | Yes. It also failed at 299 | 15:50 |
| ZipCPU | You've also got a problem with your had_been_enabled logic. It fails at line 440. | 15:58 |
| ZipCPU | Looks like a reset is messing that up. | 15:58 |
| ZipCPU | promach_: You don't have your resets properly tied together, now, do you? | 15:59 |
| promach_ | tied together ? that is not realistic in real life | 15:59 |
| promach_ | there must be clock phase difference between tx_clk and rx_clk in real life | 16:00 |
| ZipCPU | I just got a failing trace from your code where the rx reset was held at one for the entire trace ... | 16:00 |
| ZipCPU | When the tx reset was asserted, the entire design failed. | 16:00 |
| promach_ | we have different trace | 16:01 |
| promach_ | my reset_tx is not asserted at all in my trace | 16:02 |
| promach_ | and reset_rx is not held at one for the entire trace | 16:03 |
| ZipCPU | I set the induction depth to 250 to get that trace. It seems to happen with a length of 200 as well. | 16:03 |
| promach_ | ok, let me solve that line 440 first | 16:06 |
| promach_ | strange, I have passed induction at length 200 before | 16:06 |
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