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| mattvenn | I remember when I had sram issues with the blackice mystorm board | 11:17 |
|---|---|---|
| mattvenn | I had unstable behaviour on the fpga because the fpga and the sram were both trying to drive the same pins | 11:18 |
| mattvenn | because there wasn't enough time for the pin direction to change | 11:18 |
| mattvenn | I wonder if something similar is happening with the hyperram on the 8 data pins | 11:18 |
| mattvenn | running it slower should resolve it | 11:19 |
| keesj | is http://www.clifford.at/yosys/download.html perhaps a bit outdated on ubuntu 18.04 yosys is already in the discto and adding the ppa results in https://pastebin.com/Wt6sdftR | 11:24 |
| tpb | Title: Yosys Open SYnthesis Suite :: Download (at www.clifford.at) | 11:24 |
| daveshah | keesj: beware that the version of Yosys in ubuntu is very old | 11:25 |
| daveshah | I would always recommend building from source following the instructions at http://www.clifford.at/icestorm/ | 11:25 |
| tpb | Title: Project IceStorm (at www.clifford.at) | 11:25 |
| cr1901_modern | I wish my build improvements PR would be accepted... :( | 11:29 |
| cr1901_modern | And well fixing yosys-smtbmc to work on Windoze PR too | 11:30 |
| keesj | ok | 11:30 |
| daveshah | cr1901_modern: clifford's pretty busy right now. ping him again and he'll look at them I'm sure | 11:31 |
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| cr1901_modern | Fair enough. It's low priority, I just mainly wanted to knock off a few bullets off my todoist :P | 11:32 |
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| mattvenn | well slowing it down makes it behave. And I think I might be right about the ram and fpga both driving the same lines at once | 13:48 |
| mattvenn | here's clk, data and direction at 3mhz system clk = 0.75mhz ram clock | 13:48 |
| mattvenn | https://imagebin.ca/v/49uDxynENjfI | 13:48 |
| mattvenn | and this one is when the serial breaks and things start going crazy. | 13:49 |
| mattvenn | 6mhz = 1.5mhz ram clock | 13:49 |
| mattvenn | https://imagebin.ca/v/49uERKOqnBFs | 13:49 |
| mattvenn | you can see the bidirectional signals now have intermediate levels | 13:49 |
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| mattvenn | so my question is, how can this part be used with the h40 chips at higher clock rates? | 13:50 |
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| ZipCPU | What is icetime giving you? | 14:08 |
| mattvenn | 90mhz | 14:15 |
| ZipCPU | And it's only working successfully at 6mhz? | 14:16 |
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| mattvenn | 0.75mhz it seems to work | 14:26 |
| mattvenn | anything higher than that and the fpga and the sram both try and drive the inout lines at once | 14:26 |
| mattvenn | which them seems to result in strange behaviour | 14:26 |
| ZipCPU | Hmm ... sounds like the controller is buggy. Is there an output enable wire? Are you watching that one? | 14:27 |
| mattvenn | I think I need to take another step back | 14:30 |
| mattvenn | I still have problems with the serial comms event at this low speed | 14:31 |
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| elms | daveshah: I'm adding ability to track symbols in hlc. Any opinion on hlc syntax? I was thinking "wire .sym> symbol" (eg "span4_y1_g7_1 .sym> vec0[1]") | 21:45 |
| daveshah | elms: haven't really worked with hlc | 21:46 |
| daveshah | I agree symbols are a good idea, that seems a reasonable enough implementation | 21:47 |
| elms | That's good enough for me to create a PR. Thanks. | 21:47 |
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