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| mattvenn | I'm having a problem with a fairly simple design | 15:31 |
|---|---|---|
| mattvenn | I'm testing Kevin Hubbard's hyperram double pmod board with his module hyper_xface.v | 15:32 |
| mattvenn | I've wired this up and it looks like it's working OK | 15:32 |
| mattvenn | I've put a serial interface in | 15:32 |
| mattvenn | so I can write addresses and read and write data | 15:33 |
| mattvenn | and am getting strange problems with bytes crossing serial boundaries on the way out | 15:33 |
| mattvenn | so an internal counter might get to 32, and this results in 8192 on the serial receive | 15:33 |
| mattvenn | removing the hyperram module removes this problem | 15:34 |
| mattvenn | so it looks to me like a timing issue | 15:34 |
| mattvenn | unfortunately, icetime fails with Unable to resolve delay for path ce -> ltout in cell type LogicCell40! | 15:34 |
| mattvenn | and google isn't helping too much on that | 15:34 |
| mattvenn | you can take a look at top.v here: https://github.com/mattvenn/hyperram/tree/icestick-example | 15:35 |
| tpb | Title: GitHub - mattvenn/hyperram at icestick-example (at github.com) | 15:35 |
| mattvenn | any guidance appreciated! | 15:36 |
| daveshah | mattvenn: the ce -> ltout is hopefully fixed in the latest icestorm (by funny coincidence this issue that has not surfaced for years was found a few weeks ago by someone else) | 15:36 |
| daveshah | however I wouldn't expect to see that at all in a design from arachne-pnr? | 15:37 |
| mattvenn | is it to do with with SB_IO blocks I'm using to get inout pins working? | 15:38 |
| mattvenn | yes, new icetime works with no errors - timing estimate of 105MHz, so my guess about timing isn't correct | 15:40 |
| mattvenn | my target is the icestick, with a 12Mhz clock | 15:40 |
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| mattvenn | some other strangeness. If I assign a new pin to the serial tx so I can look at it on the scope | 16:09 |
| mattvenn | output tx2 | 16:09 |
| mattvenn | assign tx2 = tx; | 16:09 |
| mattvenn | then the serial port stops functioning, no bytes ever sent | 16:09 |
| mattvenn | (with hyperram module enabled) | 16:10 |
| mattvenn | with hyperram removed - all works as expected | 16:10 |
| mattvenn | I don't really know how to progress from here | 16:10 |
| mattvenn | why would adding a new wire stop the design from working? | 16:11 |
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| maikmerten | yay, first take on a very ugly SRAM and PMOD "wing" for the HX8K breakout board... https://pasteboard.co/HvYoBXzG.png | 18:13 |
| tpb | Title: Pasteboard Uploaded Image (at pasteboard.co) | 18:13 |
| ZipCPU | mattvenn: Are you using any PLL's in your design? | 18:27 |
| elms | ice40 question, how can I configure a logic cell to use a DFF to use the CEN, but another cell in the same tile use a DFF with enable set to 1? | 18:38 |
| elms | It's not clear from http://www.clifford.at/icestorm/logic_tile.html but it looks like it should be possible in figure 2.2 of iCE40 LX/HX family datasheet | 18:40 |
| tpb | Title: Project IceStorm LOGIC Tile Documentation (at www.clifford.at) | 18:40 |
| daveshah | elms: no | 18:40 |
| daveshah | CEN of 1 is simply disconnecting the CEN to the whole tile | 18:40 |
| elms | you mean it's not possible? | 18:40 |
| daveshah | No, its not possible | 18:40 |
| elms | are the enable and output mux ganged? https://usercontent.irccloud-cdn.com/file/cVzKFFrp/iCE40-PLB.png | 18:42 |
| daveshah | Yes - I can't see any reason why you would use them separately anyway | 18:42 |
| elms | yeah, trying something with VPR and it's packing some together such that one has a cen and one is always 1. Guess we need to stop those from being packed in the same time. Thanks! | 18:44 |
| daveshah | Yes, you will need to | 18:45 |
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| mattvenn | ZipCPU: no plls | 18:48 |
| ZipCPU | Ok, then that's not your problem. | 18:48 |
| mattvenn | the only other time I've experienced things working funny on addition or removal of a wire or register was due to timing issues | 18:49 |
| mattvenn | maikmerten: looks cool! are there spare wires you can use for more pmods? | 18:50 |
| ZipCPU | mattvenn: I'm also struggling to understand what would cause your issue(s). It's not making sense here, no matter how many times I read your description. | 18:51 |
| ZipCPU | mattvenn: To understand why icetime is failing, let me ask how many clocks are being used in your design? (I know you said you weren't using any PLL's) | 18:59 |
| maikmerten | mattvenn, some pins are left, but not enought for a 2x6 PMOD | 18:59 |
| maikmerten | *enough | 18:59 |
| maikmerten | those 2x20 headers carry surprisingly few signals | 19:00 |
| maikmerten | given that there's about 10 GNDs per connector | 19:00 |
| maikmerten | *there are | 19:00 |
| maikmerten | also it's a hazzle to route signals between those pin headers to the right hand side, which explains the weird lines at the top of the board | 19:02 |
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| maikmerten | https://pasteboard.co/HvYKjGC.png | 19:06 |
| tpb | Title: Pasteboard Uploaded Image (at pasteboard.co) | 19:06 |
| maikmerten | (a pin header with 1x6 pmod signals should be doable) | 19:08 |
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| * maikmerten adds a 1x6 PMOD header to the design | 19:14 | |
| mattvenn | let me know when you put in on oshpark | 19:20 |
| mattvenn | (if) | 19:20 |
| mattvenn | ZipCPU: daveshah told me the bug had been fixed and I verified timing is OK with a new icetime | 19:20 |
| mattvenn | only one clock | 19:21 |
| mattvenn | well.. the uart generates a baud clock | 19:21 |
| mattvenn | so I guess that's another | 19:21 |
| maikmerten | mattvenn, https://pasteboard.co/HvYQQru.png | 19:22 |
| tpb | Title: Pasteboard Uploaded Image (at pasteboard.co) | 19:22 |
| maikmerten | mattvenn, sure, I'll happily share the design | 19:23 |
| mattvenn | sweet! | 19:23 |
| mattvenn | one problem I discovered using sram on the blackice board was that they'd used a global PLL pin in the i/o | 19:23 |
| mattvenn | which meant only 1 PLL could be used if the sram was being used | 19:24 |
| mattvenn | so might be worth checking the pins that would need to be inout for the sram aren't the PLL pins | 19:24 |
| maikmerten | one the hx8k breakout board the clock is on J3 | 19:25 |
| * maikmerten checks this is not used on the SRAM | 19:25 | |
| maikmerten | ewww, J3 is on header "J4", and yes, I'm currently happily using that for the SRAM | 19:27 |
| maikmerten | thanks for the hint | 19:27 |
| maikmerten | (why why why did they do that?!) | 19:27 |
| mattvenn | ching! | 19:32 |
| mattvenn | https://forum.mystorm.uk/t/placement-conflict-between-sb-io-for-ram-and-pll/224/7 | 19:33 |
| tpb | Title: Placement conflict between SB_IO (for RAM) and PLL? - myStorm (at forum.mystorm.uk) | 19:33 |
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| maikmerten | yup, oscilloscope confirms a neat 12 MHz clock on for signal "J3" on header J4 | 19:35 |
| maikmerten | yup, oscilloscope confirms a neat 12 MHz clock on signal "J3" on header J4 | 19:35 |
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| maikmerten | okay, thankfully it was easy to avoid the J3 pin without a ripple effect on the signal routing | 19:41 |
| maikmerten | but my, without having this conversation I would for sure have ended up with a non-functional board | 19:42 |
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