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| promach | any particular reason why multiclock induction does not follow my assume() ? | 02:42 |
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| ZipCPU | promach: Go check your code again. Either the assumption is not being hit, or it isn't assuming what you think it is assuming. | 03:12 |
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| promach | ZipCPU: no, both situations you mentioned just now are not what causing the problem :| | 03:16 |
| ZipCPU | Is this a clocked assumption? | 03:17 |
| promach | yes | 03:19 |
| promach | ZipCPU: again, I am not trying to blame the tool | 03:19 |
| ZipCPU | Does it need to be? i.e. does it depend upon $past? | 03:19 |
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| promach | yes, it needs $past() | 03:20 |
| ZipCPU | The assertion that is failing, is it also a clocked assertion? | 03:20 |
| promach | yes | 03:20 |
| ZipCPU | Using the same clock? | 03:21 |
| promach | assume() is in @(posedge tx_clk) , assert() is in @($global_clock) | 03:21 |
| promach | I have to do this way | 03:21 |
| promach | I cannot use the same clock | 03:21 |
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| promach | https://github.com/promach/UART/blob/development/rtl/test_UART.v#L350 | 03:22 |
| tpb | Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com) | 03:22 |
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| ZipCPU | How many tx_clk's are in your induction window? | 03:22 |
| promach | what do you mean by window ? | 03:22 |
| ZipCPU | The number of timesteps or depth of the proof | 03:23 |
| promach | 150 | 03:23 |
| ZipCPU | Are you assuming an input to your core? Or logic within your core? | 03:24 |
| promach | ZipCPU: see https://github.com/promach/UART/blob/development/rtl/test_UART.v#L711 | 03:24 |
| tpb | Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com) | 03:24 |
| promach | input to the UART core | 03:25 |
| ZipCPU | Hmmm ... not very realistic is it? | 03:25 |
| promach | ? | 03:26 |
| ZipCPU | "assuming" that the external interface will hold the data constant until the UART has finished sending it. | 03:26 |
| promach | what is wrong with that ? | 03:27 |
| promach | I got what you mean now | 03:27 |
| promach | but that does not tell why the multiclock induction does not follow the assume() | 03:28 |
| ZipCPU | The assume isn't evaluated until the tx_clk timestep. If before that time the $global_clock assertions are evaluated, then you have a bit of a conflict. | 03:28 |
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| promach | you mean race condition between always block ? | 03:29 |
| ZipCPU | Basically | 03:29 |
| ZipCPU | One solution would be to use some registers to get rid of the $past operators and make it an always @(*) assumption. | 03:29 |
| promach | if(enable) reg_i_data <= i_data; | 03:30 |
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| ZipCPU | always @(posedge i_clk) past_i_data <= i_data; | 03:32 |
| ZipCPU | You've got the basic idea, we're just arguing over variable names at this point .... and the enable line. | 03:32 |
| promach | just store the data into a register when the single-pulse enable signal is asserted | 03:36 |
| promach | I got what you mean. | 03:36 |
| promach | I start to admire the beauty of always_ff | 03:37 |
| ZipCPU | Yes, but the normal $past isn't driven with an enable, but rather with a clock transition. | 03:37 |
| promach | I am not going to use $past for assume | 03:37 |
| promach | you messed up the assert and assume in this case | 03:38 |
| promach | my assert() does not use $past() | 03:38 |
| ZipCPU | I did? | 03:38 |
| promach | only assume() uses $past() | 03:38 |
| promach | see line 711 | 03:38 |
| mithro | I'm obviously missing something - as it shouldn't be this hard to write a yosys pass that does what I want :-( | 03:39 |
| ZipCPU | Yes, but reading the history on IRC ... I was referencing an assume ... | 03:39 |
| ZipCPU | mithro: Don't look at me! I've never tried writing any. ;) | 03:39 |
| mithro | ZipCPU: There is a big piece of missing documentation around things like SigPool, SigChunk, SigBit, replace/remove, how Wires and ports are related.... | 03:48 |
| mithro | And Clifford can't tell me I didn't look at the documentation, as I've got it open right here now | 03:49 |
| ZipCPU | mithro: I'd love to help, but I'm much more of a user than a developer of yosys at this point. | 03:49 |
| ZipCPU | 'n8 | 03:50 |
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| daveshah | mithro: certainly I've found as soon as I find a pass that's vaguely what I want it is easy to work out what is going on | 06:11 |
| mithro | daveshah: I sent Clifford a bunch of info were I got stuck and what I found confusing | 06:12 |
| daveshah | IMO chapter 6 of the manual looks good, although I'm not such a manual reader personally | 06:13 |
| mithro | I was looking at splitnets and deminout | 06:14 |
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| Kokjo | rqou: Hey! What kind of board are using for projectchibi? I would like to help build the tools and experiment with the MAX V CPLD's. | 09:01 |
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| rqou | Kokjo: unfortunately I currently don't actually have a board! | 09:04 |
| rqou | everything that has been done has been done with only software | 09:05 |
| rqou | however, i have designed a custom board that's currently somewhere in the mail, so i expect to be able to do hardware testing soon | 09:05 |
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| elms | I'm hoping someone can enlighten me about some special cases in icetime. https://github.com/cliffordwolf/icestorm/blob/master/icetime/icetime.cc#L835-L847 I'm getting some errors with a picosoc using symbiflow "Unable to resolve delay for path ce -> ltout in cell type LogicCell40!" Also see that I can get "sr -> ltout" | 16:42 |
| tpb | Title: icestorm/icetime.cc at master · cliffordwolf/icestorm · GitHub (at github.com) | 16:42 |
| elms | daveshah: ^^ are you familiar with icetime? | 16:43 |
| daveshah | elms: it might be a bug in the LutCascade stuff, given arachne-pnr didn't use it it might not be that well tested | 16:44 |
| daveshah | neither ce -> ltout nor sr -> ltout exist as paths, because ltout is a combinational output of the LUT only | 16:44 |
| daveshah | can you share a test case please? | 16:44 |
| elms | right now it involves checking out try-picosoc2 branch of vtr and symbiflow-arch-defs. I can share the asc file if that would be helpful | 16:46 |
| daveshah | Please just send an asc file | 16:47 |
| elms | https://usercontent.irccloud-cdn.com/file/W4kYVPEG/hx8kdemo.asc | 16:50 |
| daveshah | Thanks | 16:51 |
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| daveshah | elms: fixed in https://github.com/cliffordwolf/icestorm/pull/175. Thanks for the test case and report! | 16:56 |
| tpb | Title: Sign in to GitHub · GitHub (at github.com) | 16:56 |
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| elms | daveshah: thanks for the fast response. Should it also bypass for lcout like the previous https://github.com/cliffordwolf/icestorm/pull/175/files#diff-5a25132493a8f47f1c5277f3a4401e8cR844 | 16:59 |
| tpb | Title: icetime: Remove non-existent paths from ce/sr to ltout by daveshah1 · Pull Request #175 · cliffordwolf/icestorm · GitHub (at github.com) | 16:59 |
| daveshah | elms: no | 16:59 |
| daveshah | lcout is the output after the flipflop (in fact the LUT/ff selection mux) | 16:59 |
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| daveshah | in that case, the only input that doesn't drive lcout is the carry input which only drives the dedicated carry chain carry output | 17:00 |
| elms | ok. Thanks again. Well that helps with icetime. Now to figure out what else is wrong as taking it back to verilog the simulation looks all wrong. | 17:03 |
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| mithro | Is there a way to loop over everything in a selection? | 20:49 |
| mithro | Seems like my best option is to go to tcl? | 20:50 |
| mithro | (Or C++) | 20:50 |
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| mithro | daveshah: Have you seen any examples of tcl in yosys? | 20:59 |
| daveshah | mithro: other than trying it once back while considering options for the VPR XML stuff, not really | 21:03 |
| mithro | Okay | 21:04 |
| mithro | I think I'm slowly figuring it out | 21:04 |
| daveshah | Not much of a Tcl fan myself, but it was handy in Project Trellis | 21:09 |
| daveshah | On the Lattice side | 21:09 |
| daveshah | Unfortunately their Tcl console had terrible memory leak issues | 21:10 |
| mithro | Hrm -- add -input "${p}_I" 1 seems to be creating a new input with the name "${p}" | 21:11 |
| daveshah | mithro: what happens without the quotes? | 21:13 |
| mithro | Hrm - it appears its not working the way I thought it was | 21:20 |
| mithro | daveshah: How do I get something from a select into tcl? | 21:20 |
| daveshah | mithro: tbh my angle of attack with vendor tcl tools has been to do all substitution and parsing in Python scripts that read and write the output :P | 21:22 |
| daveshah | It's probably a case of printing the selection and putting it into a Tcl list | 21:22 |
| mithro | I just want a loop :-P | 21:22 |
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| daveshah | mithro: so I think the first step is a select -list | 21:23 |
| mithro | set inout [select -list i:* o:* %i] | 21:24 |
| mithro | That just writes the list to stdout | 21:24 |
| daveshah | The Yosys bit of that looks good | 21:24 |
| daveshah | But maybe you have to use -write and write to a temp file then read that in | 21:25 |
| mithro | yerk... | 21:25 |
| daveshah | I tried to get this working with Lattice's tcl stuff and failed | 21:28 |
| mithro | Oh well, guess I go back to C++ | 21:28 |
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| mithro | w no Python? :-P | 21:30 |
| daveshah | There will be Python bindings for the RTLIL side of things done over the summer, IIRC | 21:32 |
| mithro | daveshah: Is there a way to just run yosys commands from C++? | 21:33 |
| daveshah | mithro: yes, that's exactly what the synth_$platform commands do | 21:34 |
| mithro | Okay, will go have a look at them | 21:34 |
| mithro | going to get coffee bblr | 21:34 |
| daveshah | e.g. https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/synth_ecp5.cc#L240 | 21:35 |
| tpb | Title: yosys/synth_ecp5.cc at master · YosysHQ/yosys · GitHub (at github.com) | 21:35 |
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