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| mithro | Is there an easy way to split inout wires into two separate wires? | 01:58 |
|---|---|---|
| mithro | Looks like you can deminout ... | 02:00 |
| mithro | An there is tribuf ... | 02:01 |
| ZipCPU | What are you trying to do? | 02:10 |
| mithro | ZipCPU: I have a module with has an inout pin - but I need it to be seperate input and output pins | 02:16 |
| ZipCPU | You'll need a tristate pin as well. | 02:17 |
| ZipCPU | Which architecture, ice40? | 02:17 |
| ZipCPU | Feel free to take a look at https://github.com/ZipCPU/icozip/blob/master/rtl/pport/ppio.v for an ice40 example if you want. | 02:18 |
| tpb | Title: icozip/ppio.v at master · ZipCPU/icozip · GitHub (at github.com) | 02:18 |
| mithro | ZipCPU: So, vpr doesn't support inout ports -- so that SB_IO needs to be separated into input/output | 02:20 |
| ZipCPU | That's what the ppio example does for you. | 02:20 |
| mithro | ZipCPU: that ppio example creates the SB_IO primitive | 02:21 |
| ZipCPU | Yes. | 02:21 |
| ZipCPU | I would prefer if the primitive were inferred. Yosys doesn't do that (yet) tho. | 02:21 |
| mithro | ZipCPU: The SB_IO primitive has a inout port - PACKAGE_PIN | 02:21 |
| ZipCPU | Yes. That's the wire that goes to the I/O pin of your device | 02:22 |
| mithro | I need to split PACKAGE_PIN into PACKAGE_PIN_I and PACKAGE_PIN_O ports | 02:22 |
| ZipCPU | I'm confused. | 02:22 |
| ZipCPU | You have two external pins? | 02:22 |
| ZipCPU | An input and an output pin? | 02:23 |
| mithro | ZipCPU: No - Verilog to Routing doesn't support inout port specifications, it models them with two seperate in/out ports | 02:23 |
| ZipCPU | Ok | 02:24 |
| ZipCPU | Most designs will have at the top level a line looking like: pin = (trien) ? out : 1'bz; | 02:24 |
| ZipCPU | Usually you can look at that line to figure out how to split the inout port. | 02:24 |
| mithro | ZipCPU: So, I need a yosys command which modifies the loaded rtl to split the PACKAGE_PIN into the two ports | 02:25 |
| ZipCPU | I'm not aware of such a command. | 02:25 |
| ZipCPU | Last I had heard, yosys only had partial support for inouts ... and that wasn't supported. | 02:25 |
| mithro | I was sure that clifford had such a command for cases were the sat solver didn't support inout either? | 02:25 |
| ZipCPU | If he did, I'd love to learn of it myself. | 02:26 |
| ZipCPU | It would make some I/O interfaces much easier. | 02:26 |
| mithro | ZipCPU: Unless I'm going crazy | 02:32 |
| ZipCPU | I'll race you to it. | 02:33 |
| ZipCPU | Crazy that is. | 02:33 |
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| TD-Linux | tinyfpga, did you have a particular header in mind to solder to the extra bottom bx pads? or are they just for wires | 06:41 |
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| tinyfpga | TD-Linux: just a standard 2.54mm pitch surface mount header | 14:45 |
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