| *** tpb has joined #yosys | 00:00 | |
| *** pie___ has quit IRC | 00:10 | |
| *** emeb has quit IRC | 00:26 | |
| *** pie_ has joined #yosys | 00:33 | |
| *** pie__ has joined #yosys | 00:33 | |
| *** emeb has joined #yosys | 00:39 | |
| *** X-Scale has quit IRC | 00:43 | |
| *** X-Scale has joined #yosys | 00:45 | |
| *** lutsabound has quit IRC | 01:07 | |
| *** emeb has quit IRC | 01:14 | |
| *** emeb_mac has joined #yosys | 01:15 | |
| *** m_t has quit IRC | 01:17 | |
| *** luismarques has quit IRC | 01:23 | |
| *** promach_ has quit IRC | 01:40 | |
| *** luismarques has joined #yosys | 01:52 | |
| *** luismarques has quit IRC | 01:57 | |
| *** kristian1aul has joined #yosys | 02:21 | |
| *** mobius_ has joined #yosys | 02:22 | |
| *** promach has quit IRC | 02:22 | |
| *** X-Scale has quit IRC | 02:22 | |
| *** pie__ has joined #yosys | 02:23 | |
| *** daddesio has quit IRC | 02:24 | |
| *** Kooda1 has quit IRC | 02:24 | |
| *** proteus-guy has quit IRC | 02:24 | |
| *** ravenexp has quit IRC | 02:24 | |
| *** lansiir has joined #yosys | 02:24 | |
| *** ravenexp has joined #yosys | 02:24 | |
| *** kristianpaul has quit IRC | 02:24 | |
| *** digshadow has quit IRC | 02:24 | |
| *** mobius has quit IRC | 02:24 | |
| *** grummel has quit IRC | 02:24 | |
| *** Max-P has quit IRC | 02:24 | |
| *** pie_ has quit IRC | 02:24 | |
| *** oldtopman has quit IRC | 02:24 | |
| *** nurelin has quit IRC | 02:24 | |
| *** digshadow has joined #yosys | 02:24 | |
| *** lansiir has quit IRC | 02:24 | |
| *** lansiir has joined #yosys | 02:24 | |
| *** nurelin has joined #yosys | 02:24 | |
| *** Kooda1 has joined #yosys | 02:24 | |
| *** Kooda1 has quit IRC | 02:24 | |
| *** ravenexp has quit IRC | 02:24 | |
| *** lansiir has quit IRC | 02:24 | |
| *** grummel has joined #yosys | 02:25 | |
| *** Kooda1 has joined #yosys | 02:25 | |
| *** ravenexp has joined #yosys | 02:25 | |
| *** proteus-guy has joined #yosys | 02:25 | |
| *** lansiir has joined #yosys | 02:30 | |
| *** lansiir has joined #yosys | 02:31 | |
| *** lansiir has joined #yosys | 02:31 | |
| *** Max-P has joined #yosys | 02:35 | |
| *** q3k has quit IRC | 03:07 | |
| *** digshadow has quit IRC | 03:13 | |
| *** pie__ has quit IRC | 03:44 | |
| *** promach has joined #yosys | 03:49 | |
| *** Max-P has quit IRC | 04:20 | |
| *** Max-P has joined #yosys | 04:21 | |
| *** digshadow has joined #yosys | 04:35 | |
| *** dys has joined #yosys | 06:40 | |
| *** emeb_mac has quit IRC | 07:00 | |
| *** dys has quit IRC | 07:51 | |
| *** X-Scale has joined #yosys | 07:56 | |
| *** ferrim has joined #yosys | 08:06 | |
| *** jwhitmore has joined #yosys | 08:07 | |
| *** luismarques has joined #yosys | 08:12 | |
| *** q3k has joined #yosys | 09:16 | |
| *** fsasm has joined #yosys | 09:49 | |
| *** jcll has joined #yosys | 09:53 | |
| jcll | hi ! Newbie here. Can I find a free ASIC oriented techfile ? | 09:54 |
|---|---|---|
| *** jwhitmore has quit IRC | 09:59 | |
| jcll | sorry. Just found the info in the doc. Thx | 10:01 |
| *** indy has quit IRC | 10:36 | |
| *** m_t has joined #yosys | 10:38 | |
| *** indy has joined #yosys | 10:42 | |
| *** jwhitmore has joined #yosys | 11:27 | |
| *** thehurley3[m] has joined #yosys | 11:36 | |
| *** AlexDaniel has quit IRC | 12:12 | |
| *** mattvenn has quit IRC | 12:26 | |
| promach | Why am I having error "SBY 20:33:19 [async_fifo] base: ERROR: No such command: read (type 'help' for a command overview)" for this line "read -formal async_fifo.sv" ? | 12:39 |
| promach | I am already using latest symbiyosys git | 12:39 |
| *** jwhitmore has quit IRC | 12:41 | |
| daveshah | promach: you need the latest Yosys git for that too | 12:42 |
| daveshah | it was only added to Yosys a couple of weeks ago | 12:43 |
| promach | oh okay | 12:44 |
| *** pippo has joined #yosys | 12:53 | |
| promach | daveshah: it seems like https://github.com/YosysHQ/yosys#setup does not work with Ubuntu 18.04 | 13:06 |
| tpb | Title: GitHub - YosysHQ/yosys: Yosys Open SYnthesis Suite (at github.com) | 13:06 |
| promach | I am using kernel 4.17.4 | 13:06 |
| promach | ./kernel/yosys.h:76:12: fatal error: tcl.h: No such file or directory | 13:06 |
| daveshah | promach: are you sure `tcl-dev` is properly installed? | 13:07 |
| promach | yes | 13:07 |
| daveshah | looking at the package contents it seemed /usr/include/tcl.h got moved to just /usr/include/tcl in newer ubuntus | 13:08 |
| daveshah | I don't use Ubuntu personally. Maybe ZipCPU is around, otherwise please open a GitHub issue (but removing the .h in the include directive should be a workaround for now) | 13:08 |
| promach | so, I will need to modify yosys.h then | 13:08 |
| * ZipCPU starts reading backlog | 13:09 | |
| ZipCPU | promach: Do you have verific installed? | 13:09 |
| daveshah | ZipCPU: tldr, Yosys seems not to build in Ubuntu 18.04 because of tcl.h | 13:09 |
| promach | no | 13:09 |
| ZipCPU | Then yosys can't process system verilog files. | 13:10 |
| promach | problem solved | 13:10 |
| promach | # include <tcl/tcl.h> | 13:10 |
| ZipCPU | That particular capabililty is part of the commercial version. | 13:10 |
| promach | daveshah: use # include <tcl/tcl.h> | 13:10 |
| ZipCPU | That would be why "read -formal async_fifo.sv" fails. | 13:11 |
| promach | ZipCPU: yup | 13:11 |
| daveshah | ZipCPU: read works with or without Verific | 13:11 |
| daveshah | it will autodetect and select the appropriate backend | 13:11 |
| ZipCPU | But SystemVerilog only works with Verific | 13:11 |
| promach | I got to go now. anyway, make is building now | 13:11 |
| ZipCPU | Sure, there are some supported non-verific pieces, but as a whole SystemVerilog requires Verific | 13:12 |
| promach | ZipCPU: https://media.readthedocs.org/pdf/symbiyosys/latest/symbiyosys.pdf#page=9 | 13:12 |
| ZipCPU | Oh, and one more ... I'm running yosys on Ubuntu 18 with no problems. | 13:12 |
| promach | [ 99%] Building abc/abc-6df1396 | 13:13 |
| promach | ERROR: ABC directory is a hg working copy! Remove abc/ and re-run "make". | 13:13 |
| promach | sigh | 13:13 |
| promach | make failed at the last step | 13:13 |
| ZipCPU | That's an easy one | 13:13 |
| ZipCPU | Find the abc/ directory (I think it's at yosys/abc) and rm -rf it. | 13:13 |
| promach | I need abc | 13:14 |
| ZipCPU | Yosys will then re-download abc from the github location, rather then the older mercurial based location | 13:14 |
| ZipCPU | The problem is that the location of the abc repository moved. | 13:14 |
| promach | ok | 13:14 |
| promach | yosys make failed again, sigh. I will start rebuilding it again tomorroew | 13:17 |
| * promach has to go now | 13:17 | |
| *** seldridge has joined #yosys | 13:21 | |
| *** m_t has quit IRC | 13:22 | |
| *** fsasm has quit IRC | 13:37 | |
| *** kristian1aul has quit IRC | 13:38 | |
| *** kristianpaul has joined #yosys | 13:38 | |
| *** promach_ has joined #yosys | 13:51 | |
| *** maartenBE has quit IRC | 13:53 | |
| *** maartenBE has joined #yosys | 13:53 | |
| *** pippo has quit IRC | 14:24 | |
| *** jcll has quit IRC | 14:39 | |
| *** seldridge has quit IRC | 15:23 | |
| promach_ | daveshah: both Ubuntu 18.04 and Arch Linux have problem installing yosys from git | 15:28 |
| promach_ | make[1]: Entering directory '/home/phung/tmp/yaourt-tmp-phung/aur-yosys/src/yosys-yosys-0.7/abc' | 15:29 |
| promach_ | make[1]: *** No rule to make target 'clean'. Stop. | 15:29 |
| promach_ | seems like abc has some changes upstream | 15:29 |
| daveshah | promach_: I am building Yosys from source (not using AUR) on Arch fine | 15:31 |
| promach_ | daveshah: you mean you "make && sudo make install" ? | 15:32 |
| daveshah | promach_: yeah, just trying with clean ABC now in case of ABC issues | 15:32 |
| daveshah | seems OK so far at least | 15:32 |
| promach_ | ok, but to make things easier for future upgrade, I would email the AUR or ABC author about this. Do you think this would be a better idea ? | 15:33 |
| promach_ | what do you mean by clean ABC ? | 15:34 |
| promach_ | daveshah | 15:34 |
| daveshah | promach_: I deleted my ABC folder so Yosys cloned it again | 15:34 |
| daveshah | but it still built fine | 15:35 |
| daveshah | I'd flag this as an AUR issue tbh | 15:35 |
| promach_ | ok | 15:35 |
| *** emeb has joined #yosys | 15:51 | |
| *** emeb has quit IRC | 15:57 | |
| *** seldridge has joined #yosys | 16:00 | |
| *** luismarques has quit IRC | 16:07 | |
| *** emeb has joined #yosys | 16:12 | |
| promach_ | daveshah: solved the AUR issue. I used the wrong AUR | 16:15 |
| promach_ | I used yosys instead of yosys-git | 16:15 |
| promach_ | For https://github.com/jbush001/NyuziProcessor/blob/master/hardware/core/synchronizer.sv#L38 , why am I having "SBY 0:07:34 [async_fifo] base: ERROR: Parser error in line synchronizer.sv:38: syntax error, unexpected $undefined" ? | 16:16 |
| tpb | Title: NyuziProcessor/synchronizer.sv at master · jbush001/NyuziProcessor · GitHub (at github.com) | 16:16 |
| promach_ | seems like yosys still does not fully support systemverilog | 16:20 |
| promach_ | I have revert the coding style to verilog | 16:20 |
| *** luismarques has joined #yosys | 16:20 | |
| *** mobius_ is now known as mobius | 16:30 | |
| *** mobius has joined #yosys | 16:30 | |
| *** tmatth has joined #yosys | 16:32 | |
| *** tmatth has left #yosys | 16:32 | |
| *** luismarques has quit IRC | 16:37 | |
| *** pie_ has joined #yosys | 16:46 | |
| *** jaafar has joined #yosys | 16:49 | |
| jaafar | tinyfpga: are you around? | 16:50 |
| tinyfpga | jaafar: what’s up? | 16:50 |
| jaafar | tinyfpga: it's Jeff from the meetup :) | 16:50 |
| jaafar | tinyfpga: didn't know if you saw my email | 16:50 |
| tinyfpga | jaafar: i saw it, just hadn’t had a chance to reply yet :) | 16:51 |
| jaafar | I know you're busy shipping! | 16:51 |
| jaafar | OK good | 16:51 |
| jaafar | I was afraid you didn't read that address :) | 16:51 |
| tinyfpga | Should finish shipping today, then I’ll be catching up on everything else | 16:51 |
| jaafar | Take your time and good luck | 16:51 |
| keesj | good luck indeed! | 16:52 |
| keesj | I am going to give a presentation at work in a few days on the fpga work I have been doing. Being able to show them something like the floorplan https://knielsen.github.io/ice40_viewer/ice40_viewer.html really helps understanding. Thank you so much for the great work | 16:54 |
| tpb | Title: ICE40 layout viewer (at knielsen.github.io) | 16:54 |
| keesj | I see this project having a huge impact | 16:55 |
| keesj | the Yosys Open SYnthesis Suite | 16:55 |
| ZipCPU | O/ | 17:03 |
| *** digshadow has quit IRC | 17:06 | |
| TD-Linux | oh wow I didn't actually know about that tool. this is way better to explain fpgas than using the xilinx p&r tool. I like how it can show all the spans | 17:08 |
| keesj | TD-Linux: to get details you have to zoom in a little https://pbs.twimg.com/media/C28FzIzWgAAzKDY.jpg for example | 17:10 |
| * knielsen wrote it exactly to understand how his designs actually worked in the fpga, especially wrt. timing | 17:11 | |
| keesj | wow .. thanks knielsen \o/ | 17:12 |
| TD-Linux | keesj, yeah I figured that out. also you can make it draw them even zoomed out with the detail slider | 17:12 |
| TD-Linux | for c+d, a, ~a does it just recognize that lut pattern? | 17:13 |
| knielsen | yeah, there is a bit of logic to recognise common logic functions. I should really add more | 17:14 |
| keesj | I am currently looking into blinky | 17:14 |
| *** promach_ has quit IRC | 17:14 | |
| TD-Linux | looks like vga has a lot of ands and nands. | 17:15 |
| TD-Linux | I do like just seeing the lut bits though :) | 17:15 |
| *** dys has joined #yosys | 17:16 | |
| keesj | I think I might be trying to get to much in one hour ... Tristan Gingold presentatin at fosdem was also a pretty good 101 https://fosdem.org/2018/schedule/event/cad_fpga_intro/attachments/slides/2136/export/events/attachments/cad_fpga_intro/slides/2136/fpga_design.pdf on the basics (and I was using VHDL in my work hence.. kinda merging different things together) | 17:18 |
| keesj | on the blinky example (that is really quite simple) why don't I see a clock or similar going to the buffers? https://i.imgur.com/Lf7OdmY.png is this something implicit? | 17:23 |
| knielsen | keesj: the clock is using one of the global nets (I think), and those are not implemented yet | 17:43 |
| knielsen | you can see the clock entering in tile (0 8), from there it's routed to a global net and the rest is implicit in current code. The Icestorm docs has the details on how the global nets work | 17:45 |
| knielsen | would be nice to see those global nets, though - might be tricky to find a way to draw them without drowning everything else though | 17:46 |
| *** digshadow has joined #yosys | 17:49 | |
| keesj | I don't see anything at (0 8) but I do see something at (0 16) called hwclk. | 17:49 |
| knielsen | right, that's the one | 17:50 |
| keesj | I think this is great enough to give a good start / idea on how things work. for myself I would like to understand a bit better but the presentation thursday so I don't have much time :P | 17:52 |
| keesj | trying to reverse a bit https://i.imgur.com/JNDWTPo.png (but also need to watch football) | 18:04 |
| *** AlexDaniel has joined #yosys | 18:07 | |
| TD-Linux | on the ice40 explorer I noticed there are massive true/false nets. what's up with that? | 18:20 |
| knielsen | TD-Linux: I think I remember seeing that - I suppose it's just using a single LUT to provide a constant "1" and then routing that everywhere (and similar for "0") | 18:22 |
| ZipCPU | There was an upgrade that was supposed to fix that. Did it ever make it downstream? | 18:23 |
| knielsen | though I can't now recall where it would need a constant 0/1 (it's been a while...) | 18:23 |
| TD-Linux | that looks like what it's doing. but... why? | 18:23 |
| TD-Linux | could just be that these are old bitstreams and a new yosys makes something better | 18:23 |
| ZipCPU | The issue was that "1" and "0" had to be created, so they were created once and then routed everywhere. | 18:24 |
| knielsen | the examples on ice40 viewer are definitely old bitstreams from a yosys probably several years old | 18:24 |
| ZipCPU | The upgrade as I recall was supposed to remove the dependency of these constants on the various LUTs. | 18:24 |
| knielsen | aha, so for example in a random place in the vga example I see a counter doing "trans_x + 1", and using a constant "1" net for an X+Y LUT function. That could just be done with a single-input X+1 LUT function, without needing the constant "1" input | 18:27 |
| knielsen | makes sense | 18:27 |
| *** digshadow has quit IRC | 18:40 | |
| keesj | knielsen: what does | 18:54 |
| keesj | O meann in a LUT? is that OR? | 18:54 |
| knielsen | doesn't it just mean constant 0 output? | 18:54 |
| keesj | I don't know . sounds plausible | 18:55 |
| keesj | no I don't think so | 18:56 |
| knielsen | sometimes only the carry output from a cell is used, and the normal output is just make constant zero | 18:58 |
| knielsen | eg. see tile (23 19) in the vga example | 18:58 |
| keesj | (in the blinky example : counter[0] enters a block and (indeed possibly the carry goes to the next block) | 18:59 |
| knielsen | yes, the small wire vertically between the luts is the carry propagation | 19:00 |
| knielsen | for some reason, apparently counter[0] and counter[1] flip-flops were synthesised/placed separately from the others. I guess one might need to check the icebox_explain output in detail to get all details | 19:04 |
| knielsen | the exact logic for how LUT functions are rendered are found here: https://github.com/knielsen/ice40_viewer/blob/master/lutfunction.js | 19:04 |
| tpb | Title: ice40_viewer/lutfunction.js at master · knielsen/ice40_viewer · GitHub (at github.com) | 19:04 |
| knielsen | hm, nifty bot... | 19:05 |
| *** ferrim has quit IRC | 19:05 | |
| *** pie_ has quit IRC | 19:12 | |
| keesj | I think I was looking at it the wrong way https://i.imgur.com/JNDWTPo.png (the a +b ) of counter 0 also acts as a flip flop). I will look at the js later | 19:13 |
| *** seldridge has quit IRC | 19:50 | |
| *** seldridge has joined #yosys | 20:02 | |
| *** seldridge has quit IRC | 20:14 | |
| *** mjoldfield has quit IRC | 20:51 | |
| *** seldridge has joined #yosys | 20:54 | |
| *** seldridge has quit IRC | 21:19 | |
| *** luismarques has joined #yosys | 21:27 | |
| *** mjoldfield has joined #yosys | 21:35 | |
| *** dxld has quit IRC | 21:41 | |
| *** dxld has joined #yosys | 21:45 | |
| *** digshadow has joined #yosys | 22:12 | |
| *** dys has quit IRC | 22:24 | |
| *** luismarques has quit IRC | 22:25 | |
| *** proteus-guy has quit IRC | 23:53 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!
