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| promach | daveshah: For my Ubuntu 18.04 yosys "make", I have "/usr/bin/x86_64-linux-gnu-ld: cannot find -ltcl8.5" , but my system had tcl 8.6 installed | 02:25 |
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| promach | is this a small bug in yosys makefile ? | 02:25 |
| promach | However, I found "LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32" in the Makefile | 02:26 |
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| mithro | daveshah: Is there an easy place to get the name of all the "primitives" inside yosys? | 18:09 |
| keesj | how many input/outputs does a simple lut have? | 18:09 |
| mithro | keesj: Depends on the architecture - LUT4 for ice40, LUT6 for most modern Xilinx stuff | 18:10 |
| daveshah | mithro: the fine-grained cells are here: https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v | 18:11 |
| tpb | Title: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com) | 18:11 |
| daveshah | need to find the coarse-grained ones | 18:11 |
| daveshah | here they are: https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v | 18:11 |
| tpb | Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com) | 18:11 |
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| mithro | daveshah: Thanks! | 19:00 |
| daveshah | mithro: FYI, you can also type 'help <cell name>' to see info about a particular cell | 19:04 |
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| keesj | I wonder why simcells.v | 19:25 |
| keesj | does not have any thing with multipl outputs (e.g. the carry discussed yesteday) | 19:26 |
| keesj | does this happen during the mapping or similar? | 19:26 |
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| daveshah | keesj: those are primarily intended as a generic ASIC synthesis cell library, although the DFF primitives there are used for fpga synthesis too | 19:37 |
| daveshah | The iCE40 specific cells are in https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v | 19:38 |
| tpb | Title: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at github.com) | 19:38 |
| daveshah | Note that SB_CARRY only has a carry output | 19:38 |
| daveshah | arachne-pnr combines that with a LUT and FF if one exists to form an ICESTORM_LC during packing | 19:39 |
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| keesj | daveshah: thanks for the info I understand it better now | 20:26 |
| mithro | daveshah: I don't quite get the difference between $dffe and $_DFFE_ ? | 20:32 |
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| daveshah | mithro: $dffe is a coarse grain *word wide* cell, whereas $_DFFE_ is a gate level *single bit* cell | 20:35 |
| mithro | daveshah: Ahh | 20:36 |
| daveshah | $dffe also has configurable polarities, whereas for $_DFFE_s this is done using different cell types | 20:36 |
| daveshah | They will then map directly to FPGA or ASIC resources | 20:36 |
| daveshah | Chapter 5 of the Yosys Manual also has some good info on this | 20:39 |
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