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| TommyT | It's Sunday and I figured I'd try out yosys and the iCE40 stick. It works brilliantly. However ... | 00:47 |
|---|---|---|
| TommyT | ... I played around with the rot example and got a very currious result with the timing analyser. A simpler circuit times in at 169.89 MHz whereas a circuit with a two-bit longer adders reaches 245.30 MHz | 00:49 |
| ZipCPU | Wow, an iCE40 can do more than 150MHz at all? | 00:53 |
| ZipCPU | mithro: I've never used iverilog | 00:53 |
| mithro | TommyT: Take a look at the timing output network | 00:54 |
| mithro | ZipCPU: You use verilator? | 00:59 |
| ZipCPU | mithro: A little googling suggest that dumpfile isn't sufficient, you'll need dumpvars as well./ | 00:59 |
| ZipCPU | mithro: Yes, I'm a very heavy verilator user. | 00:59 |
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| ZipCPU | Although ... now that I've gotten involved in Formal, I don't do quite so much with Verilator as I used to. ;) | 01:02 |
| TommyT | @mithro: fast version "Resolvable net names on path: 0.640 ns .. 1.229 ns divider[0] ... 3.270 ns .. 3.859 ns $auto$alumacc.cc:474:replace_alu$13.C[9]" | 01:05 |
| TommyT | Total number of logic levels: 11 Total path delay: 4.08 ns (245.30 MHz) | 01:05 |
| TommyT | The simpler/slower circuit: "Resolvable net names on path: 0.640 ns .. 0.640 ns divider[8] 3.964 ns .. 3.964 ns divider[8]$2 4.413 ns .. 5.886 ns $abc$204$n6" | 01:06 |
| TommyT | Total number of logic levels: 2 Total path delay: 5.89 ns (169.89 MHz) | 01:06 |
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| TommyT | What's the right way to dig deeper? | 01:07 |
| mithro | TommyT: What icetime are you running? | 01:07 |
| TommyT | This is freshly cloned from github an hour ago | 01:07 |
| mithro | TommyT: I meant what arguments are you giving it? | 01:08 |
| TommyT | I'm following the http://www.clifford.at/icestorm/ example literally, thus I'm invoking icetime -tmd hx1k rot.asc | 01:09 |
| tpb | Title: Project IceStorm (at www.clifford.at) | 01:09 |
| mithro | TommyT: Add a -v | 01:12 |
| TommyT | Gives me "Usage: icetime ..." | 01:12 |
| TommyT | Ah | 01:12 |
| TommyT | I see, the -v doesn't mix with the other options | 01:13 |
| mithro | TommyT: Should give you a pretty detailed information on how it calculated the timing | 01:15 |
| TommyT | :) Thanks, I'd have to read up to understand that, but AFAICT, the routing is randomly worse for the simpler case. I guess that surprised me (I've never see such an extreme case with X or A) | 01:16 |
| mithro | TommyT: I guess with large cells, the difference between one and two tiles make make a big effect? | 01:18 |
| TommyT | TIL: giving arachne-pnr a -r can make a big difference. Now the simpler design hits 275 MHz. I guess I should also play with the seed | 01:21 |
| mithro | Clifford was complaining at me regarding that -- with arachne-pnr not being timing driven the seed really matters apparently | 01:21 |
| TommyT | Dramatically so apparently. Seeds 1..10 gets results all over [162;274] MHz! | 01:24 |
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