| *** tpb has joined #yosys | 00:00 | |
| *** roh has quit IRC | 00:08 | |
| *** philtor has joined #yosys | 00:36 | |
| *** roh has joined #yosys | 00:43 | |
| *** gnufan has quit IRC | 00:49 | |
| *** gnufan has joined #yosys | 00:55 | |
| *** digshadow has joined #yosys | 01:42 | |
| *** digshadow has quit IRC | 01:47 | |
| *** seldridge has joined #yosys | 01:49 | |
| *** emeb_mac has joined #yosys | 01:57 | |
| *** m_w has quit IRC | 02:03 | |
| *** digshadow has joined #yosys | 03:03 | |
| *** ZipCPU has joined #yosys | 03:33 | |
| *** seldridge has quit IRC | 03:38 | |
| *** seldridge has joined #yosys | 03:48 | |
| *** emeb has quit IRC | 04:05 | |
| *** leviathan has joined #yosys | 04:10 | |
| *** leviathan has joined #yosys | 04:11 | |
| *** seldridge has quit IRC | 05:04 | |
| *** dys has joined #yosys | 05:12 | |
| *** dxld has quit IRC | 05:39 | |
| *** dxld has joined #yosys | 05:44 | |
| *** ZipCPU has quit IRC | 06:02 | |
| *** emeb_mac has quit IRC | 06:07 | |
| *** GuzTech has joined #yosys | 06:42 | |
| *** roh has quit IRC | 07:48 | |
| *** mirage335 has quit IRC | 09:17 | |
| *** FabM has quit IRC | 09:18 | |
| *** FabM has joined #yosys | 09:21 | |
| *** roh has joined #yosys | 09:30 | |
| *** kuldeep has quit IRC | 09:30 | |
| *** kuldeep has joined #yosys | 09:30 | |
| *** mirage335 has joined #yosys | 09:39 | |
| *** xerpi has joined #yosys | 09:53 | |
| *** xerpi has quit IRC | 09:54 | |
| *** xerpi has joined #yosys | 09:54 | |
| *** kuldeep has quit IRC | 10:01 | |
| *** kuldeep has joined #yosys | 10:01 | |
| *** dys has quit IRC | 10:03 | |
| *** dys has joined #yosys | 10:04 | |
| *** leviathan has quit IRC | 10:42 | |
| *** leviathan has joined #yosys | 10:46 | |
| *** GuzTech has quit IRC | 11:00 | |
| *** GuzTech has joined #yosys | 11:00 | |
| *** pie_ has joined #yosys | 11:17 | |
| *** xerpi has quit IRC | 11:32 | |
| puddingpimp | nice, I took a second look, and managed to build yosys on FreeBSD with only one patch | 11:37 |
|---|---|---|
| puddingpimp | in verilog_parser.y, FreeBSD's version of bison-2.7.12 from 2013 can't handle %define parse.error verbose | 11:37 |
| puddingpimp | commented it out and the whole thing built | 11:38 |
| *** eightdot has quit IRC | 11:41 | |
| puddingpimp | FreeBSD won't take bison 3 for license reasons, but it's probably installable from a ports | 11:42 |
| puddingpimp | yea, devel/bison is 3.0.4 | 11:44 |
| cr1901_modern | Does bison have a define for the OS you're running on? I believe the idea is yosys should run without _requiring_ any external deps on each OS | 11:45 |
| * cr1901_modern might be wrong | 11:45 | |
| cr1901_modern | I should also test a compile on NetBSD sometime soon, but right now I only have a RPi 1 running it | 11:46 |
| cr1901_modern | yosys _should_ compile, but it'll take days when it has to go to swap lmao | 11:46 |
| puddingpimp | I'm not familiar with bison, I just did the minimal research to figure out why it was failing | 11:46 |
| puddingpimp | probably the right ifdef bracket, if that's what you're suggesting is bison version >= 3 (however that is expressed) | 11:47 |
| cr1901_modern | yes that | 11:48 |
| *** kuldeep has quit IRC | 11:48 | |
| puddingpimp | since it probably should use define parse.error verbose if the user has devel/bison installed (as it gives better debugging when hacking on the parser) | 11:48 |
| *** eightdot has joined #yosys | 11:49 | |
| cr1901_modern | %require "version" is the best I can find, but that exists w/ an error if you don't have the correct version | 11:50 |
| puddingpimp | beats me, I can't even figure out how to do a conditional compile in bison | 12:21 |
| puddingpimp | I wanted to submit a patch, but I can't figure out the right solution, so I'll proceed with the works-for-me approach of commenting out that line | 12:23 |
| puddingpimp | note, the FreeBSD install instructions in README do mention pkg install ... bison ... so if you just follow the instructions like I didn't, it should just build | 12:27 |
| *** Guest95104 has quit IRC | 12:29 | |
| *** ar3itrary has joined #yosys | 12:29 | |
| cr1901_modern | ahhh I see | 12:30 |
| puddingpimp | last time I tried building on FreeBSD, there were no instructions, and I think I had more build errors, or were just less pereserverent | 12:30 |
| *** kuldeep has joined #yosys | 12:34 | |
| *** gnufan1 has joined #yosys | 12:47 | |
| *** gnufan has quit IRC | 12:48 | |
| *** develonepi3 has joined #yosys | 12:55 | |
| *** pie_ has quit IRC | 13:25 | |
| *** dys has quit IRC | 13:46 | |
| *** pie_ has joined #yosys | 13:53 | |
| *** emeb has joined #yosys | 14:03 | |
| *** xerpi has joined #yosys | 14:08 | |
| *** xerpi has joined #yosys | 14:09 | |
| *** promach_ has joined #yosys | 14:18 | |
| *** AlexDaniel has quit IRC | 14:20 | |
| *** AlexDaniel has joined #yosys | 14:20 | |
| *** seldridge has joined #yosys | 14:26 | |
| promach_ | awygle: for your UART, did you manage to pass induction depth of 10 if CLOCKS_PER_BIT is 8 ? | 14:31 |
| promach_ | what is your induction depth during test ? | 14:31 |
| *** dys has joined #yosys | 14:32 | |
| *** m_w has joined #yosys | 15:05 | |
| *** GuzTech has quit IRC | 15:34 | |
| *** develonepi3 has quit IRC | 15:53 | |
| *** gnufan has joined #yosys | 15:55 | |
| *** gnufan1 has quit IRC | 15:58 | |
| *** swick has quit IRC | 16:12 | |
| *** pointfree1 has quit IRC | 16:13 | |
| *** fevv8[m] has quit IRC | 16:13 | |
| *** indefini has quit IRC | 16:13 | |
| *** samayra has quit IRC | 16:13 | |
| *** MatrixTraveler[m has quit IRC | 16:13 | |
| *** lok[m] has quit IRC | 16:13 | |
| *** Guest57793 has quit IRC | 16:13 | |
| *** marbler has quit IRC | 16:13 | |
| *** nrossi has quit IRC | 16:13 | |
| *** weebull[m] has quit IRC | 16:13 | |
| *** jfng has quit IRC | 16:13 | |
| *** seldridge has quit IRC | 16:13 | |
| *** ZipCPU has joined #yosys | 16:20 | |
| *** seldridge has joined #yosys | 16:30 | |
| *** roh has quit IRC | 16:35 | |
| *** massi has quit IRC | 16:36 | |
| *** samayra has joined #yosys | 16:42 | |
| *** promach_ has quit IRC | 16:53 | |
| *** digshadow has quit IRC | 17:29 | |
| *** AlexDani` has joined #yosys | 17:51 | |
| *** AlexDaniel has quit IRC | 17:51 | |
| *** xerpi has quit IRC | 17:54 | |
| *** digshadow has joined #yosys | 17:55 | |
| *** AlexDani` is now known as AlexDaniel | 17:56 | |
| *** emeb has quit IRC | 18:30 | |
| *** azzizi has joined #yosys | 18:58 | |
| azzizi | Hello ! Can anyone lpease checkout the imgur link: https://imgur.com/a/xs167on | 19:03 |
| tpb | Title: Help please - Album on Imgur (at imgur.com) | 19:03 |
| azzizi | May I know why initially there are subsequent attribute wire attribute wire lines ? | 19:04 |
| daveshah | azzizi: in this case, the attributes say which source line each wire came from | 19:05 |
| daveshah | They are intended for diagnostics, primarily | 19:05 |
| azzizi | And may I know the meaning of wire width 32 $add$new.v:22$7_Y | 19:09 |
| daveshah | That simply means a wire of width 32 and name $add$new.v:22$7_Y | 19:10 |
| daveshah | The name is merely an internally generated identifier | 19:10 |
| azzizi | Line 22 has 'count'...is it the identifier for count ? | 19:14 |
| daveshah | It might be another part of the logic generated by or related to that line | 19:15 |
| daveshah | Personally I'd avoid trying to parse the Yosys identifiers | 19:16 |
| azzizi | May I know why? RTLIL has all the information of the source code and probably I will have to parse the identifiers to know about the transitions / control flow | 19:18 |
| azzizi | <daveshah> you see anything wrong with my plan? | 19:31 |
| daveshah | I don't think identifiers are considered stable | 19:31 |
| daveshah | You should be looking at src attributes to get file and line information | 19:32 |
| daveshah | And cells for anything functional | 19:32 |
| *** leviathan has quit IRC | 19:35 | |
| azzizi | Thanks <daveshah>.........could you please look at the imgur...... "attribute \src "new.v:22" cell $add $add$new.v:22$7" these two lines in the RTLIL and the subsequent definitions of parameter and connect..any idea what they mean? | 19:55 |
| *** roh has joined #yosys | 19:55 | |
| daveshah | This instantiates a $add cell (the text after `cell` is the cell type and then name) | 19:56 |
| daveshah | The parameters specify the port widths and signedness of the add operations | 19:57 |
| daveshah | The connect tell you what the nets the ports of the adder connect to | 19:57 |
| daveshah | A and B are the adder inputs and Y the output | 19:57 |
| daveshah | The operation here is: $add$new.v:22$7_Y = count + value | 19:58 |
| *** xerpi has joined #yosys | 20:09 | |
| awygle | promach: i haven't looked at that in months, but apparently i was using 200 | 20:26 |
| awygle | with 16 CLOCKS_PER_BIT (which is OVERSAMPLING in my code) | 20:27 |
| awygle | basically for that test i selected a depth that included the whole character | 20:29 |
| awygle | but that might have been for "cover" purposes, not for induction - might have been able to pass a shorter length, i don't remember. you can try it out easily though. | 20:29 |
| *** samayra has quit IRC | 20:53 | |
| *** tinyfpga has quit IRC | 20:56 | |
| *** ralu has quit IRC | 20:57 | |
| *** ralu has joined #yosys | 20:58 | |
| *** tinyfpga has joined #yosys | 20:58 | |
| *** sklv1 has quit IRC | 21:10 | |
| *** sklv1 has joined #yosys | 21:10 | |
| *** samayra has joined #yosys | 21:16 | |
| *** ZipCPU has quit IRC | 21:31 | |
| *** digshadow has quit IRC | 21:35 | |
| *** digshadow has joined #yosys | 22:03 | |
| *** dys has quit IRC | 22:04 | |
| *** mjoldfield has quit IRC | 22:08 | |
| *** mjoldfield has joined #yosys | 22:11 | |
| *** evenzhou has joined #yosys | 22:49 | |
| *** evenzhou has left #yosys | 23:00 | |
| *** gnufan has quit IRC | 23:11 | |
| *** quigonjinn has quit IRC | 23:12 | |
| *** roh has left #yosys | 23:16 | |
| *** xerpi has quit IRC | 23:20 | |
| *** samayra has quit IRC | 23:20 | |
| *** gnufan has joined #yosys | 23:31 | |
| *** MatrixTraveler[m has joined #yosys | 23:42 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!