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| mithro | Anyone know what the .SEQ_MODE parameter in the output from icetime mean? | 00:37 |
|---|---|---|
| * cr1901_modern doesn't know the answer to any of those questions :/ | 00:42 | |
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| mithro | hey cr1901_modern | 00:58 |
| cr1901_modern | hello mithro, how's it going? | 00:58 |
| mithro | cr1901_modern: Super frustrated because I'm super close to getting things working | 00:59 |
| cr1901_modern | mithro: Hey me too! Except the super close to getting things working part | 00:59 |
| cr1901_modern | That part has evaded me | 00:59 |
| cr1901_modern | I still have crashing lm32 bitstreams on tinyfpga, and I don't know why. I even made a repo documenting crashes | 01:00 |
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| mithro | cr1901_modern: At least reproducible is good! | 01:15 |
| mithro | cr1901_modern: Want to look at my problem instead then? :-P | 01:15 |
| mithro | cr1901_modern: I'm trying to figure out why my icestorm HLC output is not logically equivalent to the input | 01:16 |
| cr1901_modern | HLC? | 01:16 |
| mithro | Not quite sure what it stands for | 01:17 |
| mithro | it's a high level description format that icestorm uses | 01:17 |
| mithro | cr1901_modern: You can seen an example here -> https://paste.ubuntu.com/p/JB9TgBD826/#23 | 01:17 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 01:17 |
| cr1901_modern | Well, if you're intimately familiar w/ ice40 internals, your problem doesn't sound all that fun either. | 01:18 |
| cr1901_modern | I wonder if there's a(n easy) way to move _just_ one SB_LUT to another location in a design, and then recompile the result to a valid bitstream | 01:19 |
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| xerpi | hi | 08:22 |
| xerpi | I'm trying to use this NAND2 gate: https://github.com/YosysHQ/yosys/blob/master/examples/cmos/cmos_cells.sp#L12 | 08:22 |
| tpb | Title: yosys/cmos_cells.sp at master · YosysHQ/yosys · GitHub (at github.com) | 08:22 |
| xerpi | the problem is that if I set A to Vdd and B to Vss, then I get "doAnalyses: Too many iterations without convergence" | 08:23 |
| xerpi | I'm using ngspice btw | 08:23 |
| xerpi | it looks like there's a problem in the node M34 (the one between the nmos transistors in series) | 08:23 |
| xerpi | any idea what's going on? | 08:23 |
| xerpi | it looks like it's because I'm using different transistor models | 08:30 |
| * sorear hasn't touched spice in years | 08:30 | |
| xerpi | hehe | 08:33 |
| daveshah | gosh, this takes me back to when I was writing a circuit simulator | 08:33 |
| daveshah | just curious, what if you tie A and B via resistors rather than directly? | 08:34 |
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| xerpi | daveshah, doesn't seem to work | 08:55 |
| daveshah | xerpi: not sure if I can suggest anything more either, haven't touched SPICE for a while either | 08:56 |
| xerpi | no worries, I think it's because my capacitance at the output is too small | 08:57 |
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| mithro | daveshah: Did something change in yosys recently -- I seem to have lost the ability to get SB_LUT4s in the output? | 14:47 |
| mithro | daveshah: Oh - a LUT1 isn't mapped to a SB_LUT4 ? | 14:48 |
| daveshah | mithro: What is your code? | 14:49 |
| mithro | https://github.com/mithro/symbiflow-arch-defs/blob/4mcmaster/tests/ice40/icelut/route-through-in1/lut.v | 14:49 |
| tpb | Title: symbiflow-arch-defs/lut.v at 4mcmaster · mithro/symbiflow-arch-defs · GitHub (at github.com) | 14:49 |
| mithro | daveshah: It gets converted to a wire rather than a LUT | 14:52 |
| daveshah | Of course it is a wire | 14:53 |
| daveshah | That statement is in no way a LUT1 | 14:53 |
| mithro | daveshah: What is a LUT1? | 14:57 |
| shapr | lookup table 1 ? | 14:57 |
| mithro | daveshah: Actually - what is the difference between a LUT1 and a wire? | 14:57 |
| daveshah | A LUT1 could be an inverter too | 14:58 |
| daveshah | Or const 0 or 1 | 14:58 |
| shapr | neat | 14:58 |
| daveshah | If you want a LUT instantiate a LUT | 14:58 |
| mithro | daveshah: Is there a specific "LUT1" primitive in Yosys? | 14:59 |
| daveshah | There might be an internal one, but you should just use an architecure primitive | 14:59 |
| mithro | architecture primitive? As in the SB_LUT4? | 15:00 |
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| mithro | https://www.irccloud.com/pastebin/ZQgWZR7j/ | 15:03 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 15:03 |
| mithro | daveshah: Should that work? | 15:03 |
| daveshah | Yep | 15:03 |
| mithro | daveshah: It doesn't :-( https://github.com/YosysHQ/yosys/issues/567 | 15:07 |
| tpb | Title: Creating a SB_LUT4 with unconnected inputs causes a C++ exception · Issue #567 · YosysHQ/yosys · GitHub (at github.com) | 15:07 |
| daveshah | mithro: clifford will look at it | 15:08 |
| daveshah | Bug in the ice40 optimisations | 15:08 |
| mithro | daveshah: Yeah | 15:09 |
| mithro | daveshah: This LUT implementation kind of looks weird... | 15:10 |
| mithro | https://github.com/YosysHQ/yosys/blob/0d636964b81ed5db4a7031a24c4b04e3bc879ad5/techlibs/common/simlib.v#L1194-L1227 | 15:10 |
| tpb | Title: yosys/simlib.v at 0d636964b81ed5db4a7031a24c4b04e3bc879ad5 · YosysHQ/yosys · GitHub (at github.com) | 15:10 |
| daveshah | Not sure, I think it's reasonable | 15:10 |
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| Groomblecom | Question about iCE40hx1k devices: how do I write verilog to synthesize a SB_WARMBOOT? | 15:12 |
| Groomblecom | As is frequently the case, I found what I was looking for after asking for help: https://github.com/cliffordwolf/icestorm/tree/master/examples/icemulti | 15:22 |
| tpb | Title: icestorm/examples/icemulti at master · cliffordwolf/icestorm · GitHub (at github.com) | 15:22 |
| Groomblecom | Follow-up question: according to the datasheets, BRAMs are not refreshed when you warmboot, unless you provide initialization data with the new config image. How do I ensure my verilog in each design gets the same BRAM? | 15:29 |
| Groomblecom | So that I can, e.g. compute a buffer with one config image, and then warmboot to a second image that processes the first image | 15:30 |
| Groomblecom | *processes data from the first image | 15:30 |
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| mithro | daveshah: Any idea why icebox_vlog didn't combined the inputs here? | 15:43 |
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| daveshah | mithro: Verilog? | 16:29 |
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