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| cr1901_modern | (Rhetorical) Is it normal for "icebox_vlog -l" to get the pin numbers completely wrong? | 13:13 |
|---|---|---|
| cr1901_modern | _none_ of them match the pcf | 13:13 |
| cr1901_modern | Oh I see, my icebox_vlog is too old | 13:17 |
| daveshah | yes, just fixed that a few days agp | 13:20 |
| daveshah | *ago | 13:20 |
| daveshah | you can now tell it the package | 13:20 |
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| cr1901_modern | And post-PAR synth _also_ suggests my design should work | 13:30 |
| cr1901_modern | fabulous. I have no way to debug this | 13:30 |
| cr1901_modern | I'm really sick of getting in over my head. What am I supposed to do, decap and read the voltages w/ a FIB? | 13:31 |
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| tinyfpga_ | cr1901_modern: do you have your project online anywhere? | 15:42 |
| cr1901_modern | tinyfpga_: Yes, I do. Lemme push changes | 15:42 |
| cr1901_modern | I have one last thing I can try before I'm truly stumped. But of course it's the most effort | 15:42 |
| cr1901_modern | I'll do what ZipCPU does and put a logic analyzer inside (or something that can control the clock one cycle at a time) | 15:43 |
| cr1901_modern | tinyfpga_: https://github.com/cr1901/misoc-lm32-sim | 15:45 |
| tpb | Title: GitHub - cr1901/misoc-lm32-sim: Testing LiteX LM32 SoCs for bugs using Verilog simulation. (at github.com) | 15:45 |
| cr1901_modern | git submodule update and then "make TARGET=tinyfpga-soc-no-trigger" | 15:46 |
| cr1901_modern | You will get 3 .vcd files as output- one pre-synthesis, one post-synthesis, and one post-PAR | 15:46 |
| cr1901_modern | I never get uart output when I load this bitstream to FPGA | 15:46 |
| cr1901_modern | but it works in all simulations | 15:46 |
| tinyfpga_ | cr1901_modern: ok, I’ll try and take a look at it today | 15:48 |
| tinyfpga_ | cr1901_modern: which board are you using? A B2 or BX prototype? I can remember what I sent your way. | 15:54 |
| cr1901_modern | B2 | 15:54 |
| tinyfpga_ | cr1901_modern: what were you using for UART to USB? | 15:54 |
| cr1901_modern | I broke out pins 5 and 6 for another UART | 15:54 |
| cr1901_modern | (for now anyway) | 15:54 |
| tinyfpga_ | cr1901_modern: what device where you connecting to the B2 to perform UART to USB conversion? | 15:57 |
| cr1901_modern | prolific FTDI cable | 15:58 |
| tinyfpga_ | cr1901_modern: can you send a link to the product page? | 16:06 |
| cr1901_modern | tinyfpga_: https://www.adafruit.com/product/954 | 16:08 |
| tpb | Title: USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi ID: 954 - $9.95 : Adafruit Industries, Unique & fun DIY electronics and kits (at www.adafruit.com) | 16:08 |
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| mithro | Does anyone know if the models output by icetime have implementations anywhere? | 23:15 |
| mithro | anyone know if there is a way to stop yosys rotating the inputs on of a lut when outputting to a blif? | 23:38 |
| mithro | I'm assuming it is happening because of "synth_ice40 -nocarry; ice40_opt -unlut; abc -lut 4" | 23:39 |
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