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| promach | awygle: you should try lowering your induction depth for testing | 02:28 |
|---|---|---|
| promach | you should be able to see very interesting waveform | 02:29 |
| promach | which you will try a bit of time to understand | 02:30 |
| promach | and it is also worth the time because it will uncover some of the deepest bug in your logic, I pressume | 02:30 |
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| keesj | my ubuntu bionic already comes with yosys and such and I am starting to play with the icestick board. Should I first upgrade / build from sources to avoid known problems or can I expect a smooth ride? | 08:40 |
| keesj | I will just with basic stuff (and need to learn verilog anyway). | 08:40 |
| keesj | the alternative would be to use a vendor toolchain/ide for the learning part but I am prepared to do a lot of work to not have to deal with that | 08:41 |
| puddingpimp | keesj: you should probably build from git, but furthermore, you should start (learning, and every design) with a simulator like iverilog or verilator (or ModelSim etc.) | 08:48 |
| keesj | puddingpimp: thanks for the hints. I indeed plan to use and test different simulators and even write test benches | 08:51 |
| keesj | I have a few books on HDL (verilog/vhdl) and gained some experience in VHDL over the last couple of month and I am looking for a smotth transision. I expect the learning curve to be less steap now | 08:53 |
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| promach_ | awygle: what so you think about https://i.imgur.com/2efSPCQ.png and https://github.com/promach/UART/blob/development/rtl/test_UART.v#L219 ? | 16:16 |
| tpb | Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com) | 16:16 |
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