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| shapr | ZipCPU: seen this? https://hackaday.io/project/152709-itsy-chipsy-make-your-own-100-chip/details | 14:40 |
|---|---|---|
| tpb | Title: Itsy-Chipsy: Make your own $100 chip | Details | Hackaday.io (at hackaday.io) | 14:40 |
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| * ZipCPU opens the web page | 14:41 | |
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| * ZipCPU is still reading ... | 14:44 | |
| ZipCPU | Wow, yeah, that is kind of disruptive ... | 14:46 |
| daveshah | There have been some interesting discussions on twitter about this | 14:50 |
| daveshah | As this is a shared die, not just wafer, the limit of the $100 price point is that is has no IO, just shared JTAG and SPI | 14:50 |
| daveshah | But the more expensive larger blocks have IO I think | 14:51 |
| ZipCPU | Was that what the twitter discussions were about? I missed the context. | 14:51 |
| cr1901_modern | No I/O absolutely ruins all the fun. But it's still good for testing I imagine | 14:54 |
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| shapr | I didn't know I could get a chip made for even a few thousand | 15:05 |
| awygle | What price point do I have to go up to to get io? | 15:17 |
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| daveshah | The twitter thread was https://mobile.twitter.com/onchipUIS/status/988467731342200834 | 15:44 |
| tpb | Title: Twitter (at mobile.twitter.com) | 15:44 |
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| shapr | sorear: I'm giving a RISC-V lightning talk, any points you suggest I cover? | 16:01 |
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| jkiv | Q: when lattice refers to GBIN being for "high fan out", are they referring to on the PCB or within the FPGA? | 17:42 |
| jkiv | Is it just that there is dedicated silicon that make these pins more appropriate for global signals inside the FPGA? | 17:43 |
| daveshah | Inside the FPGA | 17:46 |
| daveshah | They are connected through dedicated buffers to every tile without needing to use general routing | 17:46 |
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| jkiv | Ah, perfect. Thanks! | 17:47 |
| daveshah | You don't always need to use the dedicated GBIN pins, you can also have a global buffer inside the FPGA | 17:47 |
| daveshah | That takes a signal from the FPGA (be it another IO or logic output) and connects it to a global wire | 17:47 |
| jkiv | Beautiful. I'd like to keep most of my pin usage to the outer-most on the BGA if I can help it :) | 17:52 |
| jkiv | Though, the GBINs aren't that deep toward the middle | 17:53 |
| jkiv | Thanks | 17:53 |
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| sorear | shapr: not really? I mean if it’s a lightning talk you have to skip a bunch anyway | 18:14 |
| shapr | fair enough | 18:15 |
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| mithro | Anyone seen https://github.com/funningboy/uvm_axi ? | 23:03 |
| tpb | Title: GitHub - funningboy/uvm_axi: uvm AXI BFM(bus functional model) (at github.com) | 23:03 |
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