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| mithro | ZipCPU: it gets optimised down to 6 LUTs if I understand correctly... | 01:49 |
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| daveshah | mithro: putting `(* keep *)` on all the submodules should work | 06:37 |
| daveshah | Otherwise, I think there's a way of running abc on the submodules rather than the flattened design, by running hierarchy after abc | 06:38 |
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| mithro | daveshah: Well, ideally I would like a design which /can't/ be optimized away | 14:59 |
| mithro | daveshah: I feel like maybe you could use a SAT solver to fill in the LUT init pattern to make sure? | 14:59 |
| ZipCPU | That was what the reddit/yosys article discussed, "Keep duplicate FF through Opt_merge". Clifford demonstrated in the response that you could keep ABC from optimizing sections of your design via the (* keep_hierarchy *) attribute. | 15:00 |
| mithro | ZipCPU: Yeah - knew about the keep stuff - but I was more looking for something that can't be optimized away... | 15:03 |
| daveshah | That design will always be optimised unless the optimiser is broken | 15:04 |
| daveshah | No SAT solver will help with that | 15:04 |
| daveshah | Either you need more inputs or a keep command | 15:04 |
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| mithro | daveshah: Out of interest how would you "prove" that? | 15:05 |
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| daveshah | Not sure TBH | 15:05 |
| daveshah | Actually, I was thinking about an arch with muxes. Too much ECP5 stuff | 15:06 |
| daveshah | Maybe there is a pattern that works | 15:06 |
| mithro | daveshah: Well, I guess you have "existence proof" -- IE ABC was able to optimize it so, therefore... :-P | 15:06 |
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| daveshah | I think this is a proof that a 6-input combinational network will produce no more than 6 LUT4s after optimisation: A 6-LUT can always be built from 4 4-LUTs and a MUX4. Proof by Yosys that a MUX4 can be built using only 2 LUT4s. Hence 6 LUT4s in total | 15:16 |
| daveshah | Feel free to point out a flaw in this | 15:17 |
| cr1901_modern | 4 4-LUTs (I can visualize a MUX4 from 2 4-LUTs just fine)? | 15:21 |
| cr1901_modern | Basically, I don't see how you get 6 bits of arbitrary functions from 4-LUTs and a MUX | 15:24 |
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| cr1901_modern | Wait nevermind. I can visualize a 5-LUT from 2 4-LUTs and a 2-MUX, so 6-LUT is just an extension of that (too lazy to actually do it in my head tho :P) | 15:26 |
| sorear | what does the MUX4 from LUT4 look like? | 15:28 |
| sorear | i couldn't figure out how to do it with less than 3 myself | 15:28 |
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| photon | any recommendation for a sequence of abc command to minimize the area? | 15:33 |
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| ZipCPU | Doesn't the "opt" yosys command do that? | 15:35 |
| photon | well, opt does not do a great job | 15:39 |
| ZipCPU | If there's another means of doing so, I'd like to find it. I've got some code I'd like optimized better .. ;) | 15:40 |
| photon | for a test design design compiler gave 160 gates and yosys/abc gave 1000 gates! | 15:40 |
| awygle | are you also running "abc"? | 15:40 |
| photon | I played abit with abc commands to reduce the number to 600 gates | 15:40 |
| photon | but, it is still far away from 160 gates | 15:41 |
| photon | reported by DC | 15:41 |
| ZipCPU | "gates" or "LUT"s? | 15:41 |
| photon | I am mapping the design to ASIC standrd cell library | 15:42 |
| ZipCPU | Does your design have RAM elements within it? | 15:42 |
| photon | if they do good job for ASIC they should for FPGA | 15:42 |
| photon | it is a pure combinational design given as a set of boolean equations | 15:43 |
| cr1901_modern | sorear: Gonna have to take a rain check on that one. My mental picture was wrong. But I imagine it can be done | 15:47 |
| sorear | cr1901_modern: i'm asking daveshah not (necessarily) you | 15:48 |
| cr1901_modern | sorear: Oh sorry, I made it all about me :P | 15:48 |
| sorear | you can answer it if you want, but I don't expect you to know details of daveshah's 2-LUT MUX4 | 15:49 |
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| daveshah | https://usercontent.irccloud-cdn.com/file/4kWC5SMZ/MUX6%20from%20LUT4s.png | 15:51 |
| daveshah | This was done using Yosys's `synth_ice40` and `show` commands | 15:52 |
| daveshah | It's a beautifully tricky solution | 15:54 |
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| cr1901_modern | Oh, I almost got it right (forgot to feed in 1:1-0:0 to the _first_ 4-LUT as well as the second) | 15:56 |
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| sorear | ahahahahahahahahha | 16:03 |
| sorear | that is amazing | 16:03 |
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| daveshah | NB - in Yosys notation y:x - b:a maps bits y..x to bits b..a - so 1:1-0:0 means select bit 1, for example | 16:09 |
| daveshah | It's a bit of an odd notation, but it's also flexible | 16:09 |
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| shapr | The ice40 boards for my novena shipped from austria, that'll be fun. | 17:29 |
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| emeb | ice40 in a novena? doesn't novena already have an FPGA in it? | 20:35 |
| sorear | Yes but it’s not usable with FOSS | 20:37 |
| shapr | emeb: https://www.jamiecraig.com/novena-ice40-add-on/ | 20:44 |
| tpb | Title: Novena iCE40 Add-On | Jamie Craig (at www.jamiecraig.com) | 20:44 |
| emeb | Yeah - not being able to run the Spartan tools on the Novena is a PITA. | 21:00 |
| emeb | I built a little RPi "hat" with an Ultra-Plus on it and it's fun to build the bitstream right on the RPi. | 21:01 |
| emeb | Even works on an RPi Zero. | 21:01 |
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