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| bthom | Hi, Is it possible to get from yosys the maximum level of logic between every dff? (In it's internal cell representation) I was considering computing it myself based on the graph output, but I thought this functionality may already be implemented in a part that I did not find in the doc. | 19:00 |
|---|---|---|
| ZipCPU | You mean ... like the longest path length? | 19:14 |
| ZipCPU | Are you asking regarding an ice40, or some other chip? | 19:15 |
| bthom | Yes the longest path length, but not for ice40, for the "Internal cell" that are described in the documentation of yosys. (So before using the final libraries, if I understand a bit the flow of yosys) | 20:15 |
| ZipCPU | Yeah, not sure I know that answer. | 20:53 |
| ZipCPU | bthom: Would "ltp" (longest-topological path) work for your purpose? | 21:05 |
| ZipCPU | -noff will exclude FF cell types | 21:05 |
| ZipCPU | ... and you'll probably want to flatten your design first. | 21:06 |
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| bthom | That sounds great! Thanks for the tip, I will try it out right now | 21:29 |
| bthom | *hint | 21:29 |
| bthom | That works great, thank yoU! | 21:31 |
| ZipCPU | I love taking credit for what other people do ... :D | 21:33 |
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