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| mithro | _florent_: Mind if I just merge https://github.com/enjoy-digital/litex/pull/13 ? | 10:23 |
|---|---|---|
| tpb | Title: Raise AttributeError. by mithro · Pull Request #13 · enjoy-digital/litex · GitHub (at github.com) | 10:23 |
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| mithro | _florent_: working on getting Bertl from apertus up and running with opsis-soc/litex | 11:02 |
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| cr1901_modern | mithro: This warning doesn't actually occur for me in mimasv2_base_lm32: https://logs.timvideos.us/%23timvideos/%23timvideos.2016-12-22.log.html#t2016-12-22T21:56:51 | 18:00 |
| mithro | I haven't checked recently.... | 18:01 |
| cr1901_modern | Okay, just was letting you know :) | 18:02 |
| cr1901_modern | mithro: You may have known this already, but the CPU actually *is* executing instructions. I suspect what is happening is that the BIOS is crashing. This is starting to mirror a bug I had when trying to get MiSoC to boot on a Spartan 3 200A with a modified LM32 (no D-cache) | 19:28 |
| cr1901_modern | i.e. your SPI flash impl works, but the CPU doesn't like something else | 19:29 |
| cr1901_modern | mithro: Confirmed it's crashing in the first printf() | 20:12 |
| _florent_ | mithro: sorry wasn't around, good for Bertl playing with opsis-soc/litex :) | 20:26 |
| cr1901_modern | Need to check where the stack pointer is being initialized to | 20:27 |
| cr1901_modern | okay it's initialied to the end of SRAM, that's correct. Now why would the CPU be crashing... | 20:30 |
| _florent_ | cr1901_modern: you are debugging the bios executed from the SPI flash? | 20:36 |
| cr1901_modern | _florent_: Correct | 20:53 |
| cr1901_modern | The BIOS crashes in printf, before any characters are written... | 20:54 |
| cr1901_modern | I know this b/c I set a write to the Mimas LEDs on return, but they never light up | 20:54 |
| cr1901_modern | *before* the printf, however, the LED write is honored | 20:54 |
| cr1901_modern | I have a few things left to try... | 20:56 |
| cr1901_modern | stack usage looks fine | 20:56 |
| mithro | cr1901_modern: I think I was seeing an effect where reading from the same address (on the SPI flash) multiple times was getting different data. | 21:25 |
| cr1901_modern | mithro: This was from the scope target? I'll check. | 21:42 |
| mithro | cr1901_modern: yeah, but I'm very uncertain | 21:44 |
| cr1901_modern | Obviously at least one of printf's children is going to have iteration. It's plausible that printf is the first place that the ROM depends on, well, the data at a specific address not changing when read :P | 21:44 |
| cr1901_modern | mithro: At the very least, I can confirm that the CPU is running, even if it's crashing | 21:44 |
| mithro | Yeah, add some loops :-P | 21:44 |
| mithro | Single step the CPU? | 21:45 |
| mithro | It would be good to have the JTAG<->gdb bridge stuff working for debugging things like this | 21:46 |
| cr1901_modern | mithro: As a last resort, I've thought about that. LM32 has JTAG support for spartan 6 | 21:46 |
| mithro | Jinx | 21:47 |
| cr1901_modern | Ihah | 21:47 |
| cr1901_modern | Another option would be to clock gate the CPU via a litescope core | 21:47 |
| mithro | Yeah | 21:48 |
| mithro | Or a button | 21:48 |
| mithro | Press button, go forward one cycle :-P | 21:48 |
| mithro | Might be too much button pressing | 21:48 |
| cr1901_modern | Yea, I'm gonna be there for an hour T_T | 21:48 |
| mithro | It would be good to have a gdb bridge which works with the wish bone bridge | 21:49 |
| mithro | Gdb is a much nicer interface for debugging :-) | 21:50 |
| mithro | Be back later, maybe | 21:51 |
| cr1901_modern | mithro: I'd have to think hard about how a gdb/wishbone bridge would work | 21:51 |
| cr1901_modern | B/c I'd somehow need to either gate the clock or get access to the JTAG interface | 21:52 |
| cr1901_modern | like I said tho. Not all options exhausted yet | 21:52 |
| mithro | Take a look at the adv debug JTAG task | 21:53 |
| mithro | Not necessarily right now | 21:53 |
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