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| -_whitenotifier-4- [symbiflow-arch-defs] dependabot-preview[bot] opened issue #2110: Dependabot couldn't find the submodule third_party/fasm - https://git.io/Jm0RT | 05:13 | |
| -_whitenotifier-4- [symbiflow-xc-fasm2bels] mbpeterson70 opened issue #53: Unconnected CARRY4s - https://git.io/Jm01f | 05:35 | |
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| umarcor | anyone can answer some specific question about how are "generic modules" managed between Surelog and Yosys? | 11:25 |
|---|---|---|
| umarcor | when combining GHDL and Yosys, generic VHDL components are completely elaborated by the VHDL frontend. therefore, it's not possible to override them through Verilog parameters. | 11:26 |
| umarcor | in some sense, the VHDL modules are fully resolved netlists (as if it was an EDIF). | 11:26 |
| umarcor | I wonder if Surelog/UHDM do the same, or they allow passing semi-elaborated components to the backend. | 11:27 |
| lambda | as far as I can tell, RTLIL::Module has a method derive() that takes a list of parameters, creates a new non-parametric module and returns its name | 11:34 |
| sf-slack | <kgugala> I think @tgorochowik may help here | 11:35 |
| umarcor | is there no type conflict/conversion required at all? that is, all SV types have exact Verilog type matches? | 11:35 |
| umarcor | (i'm rather ignorant about SV) | 11:35 |
| sf-slack | <tgorochowik> in general it is not possible to override anything in yosys when using surelog | 11:39 |
| sf-slack | <tgorochowik> i.e. surelog does the elaboration | 11:39 |
| sf-slack | <tgorochowik> if you use different params to instantiate the same module it will get a slightly different name in yosys (and will not be parameterized at this point) | 11:40 |
| lambda | compare also with the RPC frontend, which probably does something very similar but over a very simple JSON pipe | 11:40 |
| -_whitenotifier-4- [symbiflow-arch-defs] acomodi opened issue #2111: Use ubuntu-20.04 as well in GH actions - https://git.io/Jmzbp | 11:50 | |
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| -_whitenotifier-4- [actions] mithro opened issue #9: Make sure that tests are run on built packages before uploading - https://git.io/JmVwg | 18:50 | |
| -_whitenotifier-4- [actions] mithro opened issue #10: Check built Python package version makes sense - https://git.io/JmVwb | 18:51 | |
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| -_whitenotifier-4- [python-fpga-interchange] mithro opened issue #35: Setup automatic publishing packages to PyPI - https://git.io/JmwEq | 23:10 | |
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