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| -_whitenotifier-4- [python-fpga-interchange] gatecat opened issue #34: Requiring a NULL tile at (0, 0) is Xilinx-specific - https://git.io/JmkPF | 10:42 | |
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| -_whitenotifier-4- [fpga-interchange-schema] gatecat opened issue #17: Use of tilePatIdx - https://git.io/JmLcU | 11:39 | |
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| -_whitenotifier-4- [prjxray] vladoshub opened issue #1625: zynq 7015MYD-C7Z015 board - https://git.io/JmGsJ | 16:39 | |
| -_whitenotifier-4- [prjxray] vladoshub opened issue #1626: zynq 7015 | MYD-C7Z015 board - https://git.io/JmGGJ | 16:40 | |
| -_whitenotifier-4- [symbiflow-arch-defs] donn opened issue #2108: TinyFPGA BX Bitstreams don't appear to work - https://git.io/JmGPv | 16:58 | |
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| -_whitenotifier-4- [sv-tests] hzeller opened issue #1400: Missing define found in verilog config *.vlt in Ibex trips some parsers - https://git.io/JmnxS | 19:03 | |
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