Wednesday, 2020-08-12

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ske33hi, sorry, anyone to help me with these points ; thanks so much02:10
ske33for ../settings/Artix7_50t.sh,02:11
ske33 1.   Can I check what is the relationship between XRAY_ROI_GRID_X1/X2 with respect to XRAY_ROI_TILEGRID?02:11
ske33      Similarly what is the relationship for XRAY_ROI_GRID_Y1/Y2 with respect to XRAY_ROI_TILEGRID?02:11
ske33      example, in the script:02:11
ske33      XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 ..."02:11
ske33      How do I set XRAY_ROI_GRID_X1/X2 and XRAY_ROI_GRID_Y1/Y2?02:11
ske33 2.   What is the relation between XRAY_ROI_TILEGRID and XRAY_ROI?02:11
ske33      what was seen in the script:02:11
ske33      XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 ..."02:11
ske33      XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 ..."02:11
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litghostThose are unused variables15:59
litghostFor the general fuzzers16:00
sf-slack<cwl11> @litghost Yes, but say for example when only inputs A2 and A1 are the only wired inputs. When trying to manually change the lookup table in my bitstream, A2,A1 = LUT[63],  A2,!A1=LUT[62], !A2,A1=LUT[61], !A2,!A1=LUT[60]. Its like the highest possible input for the LUT gets shifted to the MSB of the LUT17:43
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litghostcwl11: So you are not thinking about how the hardware functions quiet right.  The 7-series LUT is always a LUT6_2, no matter the width of the equation being implemented21:20
litghostcwl11:  LUT.INIT[{A5,A4,A3,A2,A1}] = O5 and LUT.INIT[{A6,A5,A4,A3,A2,A1}] = O6 is always true21:20
litghostcwl11: When mapping smaller LUT equations onto the O6 or O5 outputs, the P&R tool needs to choose how to relate the library cell pins (e.g. I0, I1 ... I5) onto the physical BEL pins (e.g. A1, A2 ... A6)21:21
litghostcwl11: It turns out that the higher pins (e.g A6 is higher than A5) have less combinatoral delay than the lower pins (A1)21:22
litghostcwl11: So a LUT2 will typically be implement using the A5 and A6 pins21:22
litghostcwl11: However the equation LUT.INIT[{A6,A5,A4,A3,A2,A1}] = O6  is still true, and depending on what signal is routed to A4 .. A1, then the equation has to change21:23
litghostcwl11: By default A1 .. A6 route to the local VCC / HARD1 site pin, e.g. a logic '1'21:23
litghostcwl11: So the relevant bits are LUT.INIT[{A6,A5,'1',1',1','1'}] = O621:24
litghostcwl11: But it is worth noting that because the 7-series CLB's support fracturing, then the equation can be more complicated if both the O6 and O5 outputs are in use, because rather than have the other pins as '1', then are "don't-care", e.g. the init bits are set such that the equations hold regardless if the unused pins are '0' or '1'21:25
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sf-slack<cwl11> @litghost Okay thank you that makes sense. So does vivado not tell me the correct inputs? When I look at the LUT6_2 in my design being used, it shows sw0 going to A3 and btn0 going to A2, and they are ORed together. But when I modify the LUT values, its as if they are going to A6 and A5. Should I just assume that smaller LUT will get shifted to have its inputs in A6 depsite what vivado shows?21:43
litghostcwl11:  Vivado has LOCK_PINS to control the behavior here21:43
litghostcwl11: The thing to pay attention here is the relationship between the cell pin -> bel pin21:44
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-_whitenotifier-3- [symbiflow-arch-defs] andrewb1999 opened issue #1636: Support multi clock region ROIs - https://git.io/JJ9zh21:53
sf-slack<cwl11> @litghost So I0 is going to A2 and I1 is going to A3.  But if there is no constraint on LOCK_PINS, they go to A6 and A5?21:55
litghostcwl11: If LOCK_PINS is not set, the Vivado router is free to remap I0/I1 to any of the 6 pins21:55
sf-slack<cwl11> @litghost Okay, thank you! I understand now21:57
sf-slack<nelson> Would like to fire up and run fasm2bels on a simple design.  Not sure what to provide for the --connection_database parameter nor how to build such a database.   Suggestions welcomed.  Will take what I learn and add installation verbiage to the README.md if that will help others.  Thanks!23:25
litghostnelson: It's a path to where to keep the database23:28
litghostnelson: If the file doesn't exist, it will create it: https://github.com/SymbiFlow/symbiflow-xc-fasm2bels/blob/0daa72301ed8ac8f963317a89eac4247822b5105/fasm2bels/fasm2bels.py#L334-L33723:28
tpbTitle: symbiflow-xc-fasm2bels/fasm2bels.py at 0daa72301ed8ac8f963317a89eac4247822b5105 · SymbiFlow/symbiflow-xc-fasm2bels · GitHub (at github.com)23:28
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