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| -_whitenotifier-c- [prjtrellis] kost opened issue #140: Add option in ecppll to generate VHDL - https://git.io/JfaT0 | 03:42 | |
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| sf-slack | <binu.praghavan> Hi, came to know about this open source project via Hackster. My experience is in FPGA design. Currently using VHDL, Python and C but have experience with Verilog. Will be keen to contribute to this project to create an open source FPGA tools platform | 09:45 |
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