Thursday, 2020-05-14

« Wednesday, 2020-05-13 Index Friday, 2020-05-15 »
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rtpgHi everyone, I'm trying to look at nMigen (someone pointed it out to me here) and in the tutorial I was pointed to GTKWave for looking at simulation results. But is there a way to see "circuit layout" like what you see in the synthesis tab kind of like with Vivado? I'm still a beginner and catch a good amount of issues just by seeing wires go to the wrong spots...02:01
rtpgapologies if this is really not the right place to ask about this kind of stuff02:01
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sf-slack2<kgugala> rtpg: what FPGA do you target and what FPGA toolchain do you use?04:51
rtpgRight now I am working off of a Xilinx Basys 3( so an Artix 7 chip?) And working off of Vivado in System Verilog. I'm trying to move to an OSS toolchain just to try and be a bit more flexible and to be able to work within something a bit more lightweight like Emacs05:05
sf-slack2<kgugala> so nMigen generates Verilog code, then you need to use FPGA toolchain to synthesize, place and route the design and generate the bitstream05:11
sf-slack2<kgugala> by default nMigen will use Vivado for Xilinx platforms05:11
sf-slack2<kgugala> if you want to use Symbiflow you can take a look on https://github.com/symbiFlow/symbiflow-examples05:12
tpbTitle: GitHub - SymbiFlow/symbiflow-examples (at github.com)05:12
sf-slack2<kgugala> there you can find some examples how to use it05:12
sf-slack2<kgugala> note that SymbiFlow is still Work In Progress, so some features may not work in your design05:13
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rtpgOK, I'll try to follow the symbiflow examples, I feel like there was a more detailed description of how to set up these examples somewhere, I'll find it again06:15
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sf-slack2<timo.callahan> Hi experts, what behavior can I expect from the xc/xc7/tests/ddr/ddr_uart.v example?   It has uart and ddr .... so can I use the tty to peek and poke locations in the dram?  i can't find any info in a README.rst or README.md.   Thanks!06:40
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sf-slack2<mkurc> @timo.callahan As far as I remember that is a LiteX DDR controller that can be issued commands through UART. Maybe ask @acomodi. I think he had been working on that some time ago.07:43
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-_whitenotifier-c- [symbiflow-arch-defs] tpagarani opened issue #1486: Quicklogic: Router run time very high - https://git.io/JfBtv08:20
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sf-slack2<acomodi> @timo.callahan This test comes from a minitest from X-Ray. Looking at the sources, there is a `scripts` directory in the test that contains the testing scripts.08:31
sf-slack2<acomodi> The python scripts send commands to the FPGA via UART which are forwarded to the DDR controller. They basically perform the calibration step. The results should look like the ones described in the prj X-Ray minitest: https://github.com/SymbiFlow/prjxray/tree/master/minitests/litex/uart_ddr/arty08:34
tpbTitle: prjxray/minitests/litex/uart_ddr/arty at master · SymbiFlow/prjxray · GitHub (at github.com)08:34
sf-slack2<kgugala> @acomodi can we add this info to readme in x-ray?08:40
sf-slack2<acomodi> @kgugala Actually this should be added in archdefs, I'll adjust the README08:43
sf-slack2<kgugala> ok08:43
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rtpgIs there a big reason for conda being what's used for distributing packages? Is it basically because these are the tools people are used to?11:16
rtpg(thinking relative to just pip/pypi, this is me following the example stuff)11:17
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sf-slack2<timo.callahan> @acomodi @kgugala, thanks! I see your commits, I'll give it a try.14:24
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sf-slack2<timo.callahan> @acomodi, I'm trying to port xc/xc7/tests/ddr to the 100t part, and I'm running into problems with prjxray_create_place_constraints.py.    You probably know that the 100t part is 4 CMTs tall rather than 3 with the 35t/50t part, and the right-hand IO banks on X1Y0 and X1Y1 are moved up to X1Y1 and X1Y2.   I've adjusted the LOC in the Verilog to adapt for that `(* LOC="IDELAYCTRL_X1Y1" *)` .   But the script seems22:45
sf-slack2to be trying to place a PLL in the new lower right corner X1Y0, and I think it should be placing it also in X1Y1.   The error is in the form of a bad key, since there are no available placements for that bel_type in that CMT: `for potential_loc in sorted(available_placements[key]):`.    This is the debug info:22:45
sf-slack2<timo.callahan> ```clock_name PLLE2_ADV_0 bel_type PLLE2_ADV self.clock_cmts[clock_name] 5 self.clock_cmts: {'$auto$iopadmap.cc:321:execute$38718': 7, '$auto$iopadmap.cc:321:execute$38723': 4, 'ibuf': 7, 'PLLE2_ADV_0': 5, 'BUFG_1': 'BOT', 'BUFG_2': 'BOT', 'BUFG_3': 'BOT', 'BUFG_4': 'BOT', 'BUFG_5': 'BOT', 'BUFG': 'TOP'} all available_placements: {('PLLE2_ADV', 4): ['PLLE2_ADV_X0Y3'], ('PLLE2_ADV', 3): ['PLLE2_ADV_X0Y2'],22:46
sf-slack2('PLLE2_ADV', 2): ['PLLE2_ADV_X0Y1'], ('PLLE2_ADV', 1): ['PLLE2_ADV_X0Y0'], ('PLLE2_ADV', 7): ['PLLE2_ADV_X1Y2'], ('PLLE2_ADV', 6): ['PLLE2_ADV_X1Y1'], ('BUFGCTRL', 'TOP'): ['BUFGCTRL_X0Y16', 'BUFGCTRL_X0Y17', 'BUFGCTRL_X0Y18', 'BUFGCTRL_X0Y19', 'BUFGCTRL_X0Y20', 'BUFGCTRL_X0Y21', 'BUFGCTRL_X0Y22', 'BUFGCTRL_X0Y23', 'BUFGCTRL_X0Y24', 'BUFGCTRL_X0Y25', 'BUFGCTRL_X0Y26', 'BUFGCTRL_X0Y27', 'BUFGCTRL_X0Y28', 'BUFGCTRL_X0Y29',22:46
sf-slack2'BUFGCTRL_X0Y30', 'BUFGCTRL_X0Y31'], ('BUFGCTRL', 'BOT'): ['BUFGCTRL_X0Y0', 'BUFGCTRL_X0Y1', 'BUFGCTRL_X0Y2', 'BUFGCTRL_X0Y3', 'BUFGCTRL_X0Y4', 'BUFGCTRL_X0Y5', 'BUFGCTRL_X0Y6', 'BUFGCTRL_X0Y7', 'BUFGCTRL_X0Y8', 'BUFGCTRL_X0Y9', 'BUFGCTRL_X0Y10', 'BUFGCTRL_X0Y11', 'BUFGCTRL_X0Y12', 'BUFGCTRL_X0Y13', 'BUFGCTRL_X0Y14', 'BUFGCTRL_X0Y15']} key: ('PLLE2_ADV', 5)```22:46
sf-slack2<timo.callahan> (I had changed the instance name to `PLLE2_ADV_0` from the original `PLLE2_ADV`)22:47
sf-slack2<timo.callahan> So there's no PLLE2_ADV in '5', which I think corresponds to X1Y0.22:48
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