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| -_whitenotifier-c- [symbiflow-arch-defs] mkurc-ant opened issue #1481: Solve the problem of automatic IDELAYCTRL placement - https://git.io/Jf845 | 12:51 | |
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| sf-slack2 | <timo.callahan> Ah, my 100t issues are my fault, due to setting XRAY_IOI3_TILES arbitrarily. I hadn't realized that this variable specifies special handling of some 50t tiles because their frame addresses are shifted one frame higher than the rest. No wonder it's messing up the programming for that one IOB. I guess I'm lucky that one of the tiles I chose for XRAY_IOI3_TILES is used in the small tests, so I ran into this | 17:25 |
|---|---|---|
| sf-slack2 | issue right away. | 17:25 |
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| daddesio | sorry if this has been asked before, but does symbiflow/prjtrellis support the SerDes on the ECP5-5G? I don't see a mention of it on the website, readme, devices.json, etc. | 19:48 |
| daddesio | I need to upload lots of data (~100Mbit) fast (~100Mbit/s) to an ARM microcontroller, and I'm wondering if that could be realistic with symbiflow in the near future. :) | 19:48 |
| daveshah | It's supported but experimental | 19:48 |
| daveshah | But it wouldn't be any use for that case, it's minimum data rate is 270Mbit/s | 19:49 |
| daveshah | At 100Mbit/s regular IO maybe with a DDR primitive would be the way to go | 19:49 |
| daddesio | have you successfully used Lattice's DDR/PCIe/ethernet cores? | 19:50 |
| daveshah | No, they are encrypted with a stupidly expensive license | 19:50 |
| daveshah | LiteX has open source DDR3 and Ethernet cores for ECP5 | 19:51 |
| daveshah | There isn't a working open source PCIe core yet | 19:51 |
| daveshah | But the basics of a PHY have been worked on: https://github.com/whitequark/Yumewatari | 19:52 |
| tpb | Title: GitHub - whitequark/Yumewatari: 妖刀夢渡 (at github.com) | 19:52 |
| daddesio | in my case I'm thinking of DMAing the data via DDR3, so my FPGA would be like a "peripheral" or slave device, then send an interrupt to the ARM chip once the upload is done | 19:54 |
| daveshah | DDR3 is working nicely with litedram | 19:55 |
| daddesio | I'll look into LiteDRAM/LiteX, thanks. | 20:08 |
| zyp | oh, I had the impression that litepcie already supported ecp5 | 20:11 |
| daddesio | (aside: the i.MX6ULL ($10 ARM SoC) has an on-chip DDR3 controller. hopefully it will play nicely :p) | 20:12 |
| daveshah | zyp: no, it doesn't, it relies heavily on the Xilinx hard PCIe IP | 20:13 |
| daveshah | daddesio: oh do you want to use the ECP5 to emulate a DDR3 memory? that is not something litedram supports | 20:13 |
| daddesio | no no, just upload lots of data (about 1GB collected over 1 second) *somewhere* the ARM chip can access at a way later time. | 20:13 |
| daddesio | (it's more like 1 GiB, not 100Mbit like I said before, now that I think about it) | 20:14 |
| daveshah | Does the ARM chip have an Ethernet PHY interface like RMII or similar? | 20:14 |
| daveshah | That can be connected "crossover" to a similar interface on the ECP5 to emulate an ethernet link between the two (and you can use raw ethernet frames, no need even for UDP) | 20:15 |
| zyp | imx6 would probably have RGMII | 20:15 |
| daddesio | I've never heard of RMII | 20:15 |
| zyp | daveshah, guess I shouldn't be in a hurry to do that m.2 board with ecp5 that I've been thinking about then :) | 20:16 |
| daddesio | and, it doesn't necessarily have to be an i.MX, it's just the first ARM chip I happened to find that has DDR3 support | 20:16 |
| zyp | daveshah, why DDR3? | 20:17 |
| zyp | daddesio* | 20:17 |
| daddesio | it doesn't have to be DDR3, I just thought it would work as an option since the ECP5 Versa supports it :p | 20:18 |
| daveshah | Shared DDR3 probably isn't a very good idea | 20:18 |
| zyp | shared DDR3 is probably very unfeasible | 20:18 |
| daveshah | I suspect it may work at low speeds if you were careful with the termination, but probably not at full speed | 20:18 |
| daveshah | And you'd need to find a way to turn off the iMX6 DDR3 interface totally while the FPGA accessed it (in particular stop the iMX from driving the CA lines) which may or may not be possible without causing other problems | 20:19 |
| daddesio | erm, I thought the DDR3 controller would have taken care of bus mastering. I guess the DDR3 controller is *just* a transceiver then? | 20:21 |
| zyp | DDR3 is not designed to be shared between multiple masters | 20:22 |
| daddesio | I must be thinking of PCIe then ? | 20:22 |
| * daddesio has never read the DDR/PCIe specs | 20:23 | |
| daveshah | PCIe is definitely not designed to be shared either | 20:24 |
| daddesio | > DDR3 is not designed to be shared between multiple masters | 20:26 |
| daddesio | I intended for the FPGA to be a slave, and the ARM chip to be the master | 20:26 |
| zyp | daveshah, apples and oranges | 20:27 |
| lambda | daddesio: how should the FPGA and MCU communicate? | 20:27 |
| daddesio | maybe I should take a step back now | 20:28 |
| daddesio | my FPGA is a logic analyzer that will collect about 1GiB of data over the course of 1 second. I'd like to save it somewhere, then do post-processing on it via an ARM chip (or maybe my laptop) | 20:29 |
| litghost | PCIe cannot be "shared", but there are ways to endpoint to endpoint communication setup via a master | 20:29 |
| litghost | e.g. DMA from a NIC to disk or vise versa | 20:30 |
| daddesio | there's no realtime requirements other than the data collection itself. I can be as slow as I want to process the data. | 20:30 |
| zyp | daddesio, in that case you'd connect the DDR3 memory or whatever directly to the fpga, and then use some other interface to read it out via the fpga | 20:30 |
| zyp | you could drop the arm chip and collect the data from your laptop via e.g. ethernet or usb3 | 20:32 |
| lambda | if you have USB3 you might even get away with streaming everything at 5Gbps, no memory required | 20:34 |
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| daddesio | alright, I admit it, that is a much easier solution. only downside is I need twice the memory (1GiB for the fpga and 1GiB for the host), but the benefit is the fpga has guaranteed low-latency write access to the DRAM. (the ECP5 only has about 468KiB of internal RAM so doesn't afford much room for jitter) | 22:23 |
| daddesio | instead of waiting around for its turn to master the (pcie) bus | 22:24 |
| daddesio | (referring to @zyp's solution) | 22:25 |
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