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| sf-slack | <kgugala> hi @ahegazy do you have any particular PR in mind? | 07:24 |
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| clay_1 | Good morning ! | 08:11 |
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| HEGAZY | @kgugala sv-tests #687 | 08:36 |
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| sf-slack | <kgugala> @HEGAZY somebody will review the PR this week (probably next 2 days) | 08:38 |
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| n45405 | hey @kgugala sv-tests #687 | 08:41 |
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| clay_1 | While trying to run the fasm2pips I run into the following errors | 09:26 |
| clay_1 | `./utils/fasm2pips.py --part xc7a35tcpg236-1 1.fasm`Traceback (most recent call last): File "./utils/fasm2pips.py", line 50, in <module> main() File "./utils/fasm2pips.py", line 46, in main ' '.join('[get_pips {}]'.format(pip) for pip in inner()))) File "./utils/fasm2pips.py", line 46, in <genexpr> ' '.join('[get_pips {}]'.format(pip) | 09:26 |
| clay_1 | for pip in inner()))) File "./utils/fasm2pips.py", line 41, in inner if pip.net_from == parts[2] and pip.net_to == parts[1]:IndexError: list index out of range | 09:26 |
| clay_1 | Could it be because my part.yaml location is not set correctly ? ( since in similar issue I had with xc7frames2bit i had to use the `part_file` argument ? | 09:28 |
| sf-slack | <kgugala> @clay_1 are you able to provide the fasm file you're trying to run through the tool? | 10:03 |
| clay_1 | here ? sure | 10:04 |
| clay_1 | its a fasm file created from the bit2fasm.py | 10:04 |
| clay_1 | https://easyupload.io/67847y | 10:06 |
| tpb | Title: Easyupload.io - Upload files for free and transfer big files easily. (at easyupload.io) | 10:06 |
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| litghost | clay_1: fasm2pips.py is an older script, and you found a latent bug in it | 13:28 |
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| clay_1 | litghost oh, I see, has it been replaced by another script ? | 14:17 |
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| litghost | clay_1: fasm2pips is just a debugging script. fasm2bels is the more complete version | 15:30 |
| litghost | clay_1: You are welcome to submit a patch fixing the bug | 15:30 |
| clay_1 | @litghost Thanks for the reply, sadly I doubt I have the skills to fix it | 15:32 |
| clay_1 | Is fasm_pprint.py an older script that is not used anymore as well ? | 15:33 |
| clay_1 | because I think it is missing a `from prjxray import util` line | 15:33 |
| litghost | clay_1: Yes | 15:39 |
| clay_1 | litghost so there is no point in reporting it as an issue, right ? | 15:40 |
| litghost | clay_1: They are worth fixing, but they aren't the primary utilities | 15:42 |
| litghost | clay_1: bit2fasm, fasm2frames, fasm2bels are all primary utilities, the others are smaller tools that have less testing and may go stale | 15:43 |
| clay_1 | litghost Okey, fasm2bels, is not in the project xray repo, right ? | 15:44 |
| litghost | clay_1: Correct | 15:45 |
| clay_1 | so I will need to get the symbiflow repo as well | 15:48 |
| clay_1 | litghost fasm2bels, needs --connection_database and --db_root arguments among others | 15:56 |
| clay_1 | so for --db_root I guess it will be something like prjxray/database/artix7/xc7a35tcpg236-1 for the xc7a35tcpg236-1 part | 15:56 |
| clay_1 | but what about the --connection_database ? | 15:57 |
| litghost | clay_1: I recommend letting the build system take care of that | 15:57 |
| litghost | clay_1: Follow the readme for examples | 15:57 |
| clay_1 | litghost I got that info from the readme | 15:58 |
| clay_1 | Invoking--------`python3 -mfasm2bels <options> <verilog> <tcl>`Required arguments are: - `--connection_database` - Path to connection database for part - `--db_root` - Path to prjxray database for part - `--part` - FPGA part - `--fasm_file` - Path to FASM file to process - verilog - Path to verilog file to write - tcl - Path to TCL file to write | 15:58 |
| litghost | Wrong README: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/README.md | 15:59 |
| tpb | Title: symbiflow-arch-defs/README.md at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 15:59 |
| clay_1 | litghost I had followed that untill the `make all_conda` part | 16:00 |
| clay_1 | so for 7 series I should do the `make all_xc7` as well before trying anything? | 16:00 |
| litghost | "make dram_test_64x1d_vivado" would be a good example, per the docs | 16:02 |
| litghost | It makes use of fasm2bels | 16:02 |
| clay_1 | ok I will try it, thank you litghost | 16:02 |
| clay_1 | litghost I got the following | 16:48 |
| clay_1 | make[1]: *** No rule to make target 'dram_test_64x1d_vivado'. Stop. | 16:48 |
| clay_1 | Makefile:28: recipe for target 'dram_test_64x1d_vivado' failedmake: *** [dram_test_64x1d_vivado] Error 2 | 16:48 |
| litghost | When you ran cmake did it warn about not having Vivado? | 16:49 |
| clay_1 | hmm I dont remember that. The fsm2bel script will make use of vivado ? | 16:50 |
| clay_1 | I thought It would give tcl + verilog and then I would have to import them to vivado manually | 16:50 |
| litghost | The target "dram_test_64x1d_vivado" generates then verilog + tcl and then feeds them into Vivado | 16:51 |
| clay_1 | ohhh | 16:51 |
| clay_1 | is it possible to skip the last part ? | 16:51 |
| litghost | Yes, run "dram_test_64x1d_bit_v" | 16:52 |
| clay_1 | great, will try it right away | 16:52 |
| clay_1 | litghost I ran that with no errors. The output files it gave are the top_bit.v and top_bit.v.tcl ? | 16:57 |
| litghost | Yes | 16:58 |
| litghost | If you want to see the commands run, "make VERBOSE=1 <target>" works nicely | 16:58 |
| clay_1 | nice :) | 16:58 |
| clay_1 | in target I put an xc7 part name ? | 16:59 |
| litghost | No, like "dram_test_64x1d_bit_v" | 17:00 |
| clay_1 | litghost thanks, I dont see running the fasm2bels in the verbose output though | 17:07 |
| litghost | You already built the outputs, so make isn't running it anymore | 17:07 |
| litghost | Remove the outputs, etc etc | 17:07 |
| clay_1 | oh ok thanks I will try it | 17:08 |
| clay_1 | litghost are all the files in the folder artix7-xc7a50t-basys3-roi-virt-xc7a50t-basys3-test generated from the test ? | 17:28 |
| litghost | Yes | 17:28 |
| clay_1 | thanks | 17:29 |
| -_whitenotifier-3- [sv-tests] ahegazy opened issue #688: Convert Atest cases - https://git.io/JvK01 | 17:36 | |
| clay_1 | litghost if I replace the file top.bit.fasm with a .fasm file I create from bit2fasm.py and then delete the top_bit.v and top_bit.v.tcl will it efectively recreate them from the fasm file I inputed ? | 17:41 |
| litghost | That would work, but is kind of round-about way to do it | 17:42 |
| litghost | But yes | 17:42 |
| clay_1 | yeah I am trying to find a way to make it work, in the fasm2bel line a lot of things are beeing defined | 17:43 |
| clay_1 | what confuses me a bit is the folder title `-xc7a50t-basys3` | 17:46 |
| clay_1 | while in the comands I see `--part xc7a35tcpg236-1` | 17:47 |
| clay_1 | so do the 35t and 50t basys 3 have actually the same files or something like that ? | 17:48 |
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| litghost | All Yes | 17:49 |
| litghost | Yes | 17:49 |
| clay_1 | nice, thanks for the clarification :) | 17:49 |
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| HEGAZY | Hi all, | 19:05 |
| HEGAZY | I've been lurking around the project and this IRC channel log for a couple of days now till i got the grasp for what's going on, I'm interested in joining you this year in Gsoc, I am a 4th year electronics Engineering student. | 19:05 |
| HEGAZY | I was an intern at mentor graphics last November worked on writing VHDL, Verilog, systemverilog testcases for the new checks in Questa lint tool, basically like what's happening in the sv-tests repo, plus validating them against customer designs like arm, amd, riscv etc and automating this using scripts | 19:05 |
| HEGAZY | I have implemented AES encryption in verilog and wrote a testbench for it using UVM : github.com/ahegazy/aes | 19:06 |
| HEGAZY | my github has multiple HDL projects that i created and other projects too, take a look if you have time: https://github.com/ahegazy?tab=repositories , this is my linkedin: linkedin.com/in/ahegazi/ (would be love to connect you guys there). | 19:06 |
| tpb | Title: ahegazy (Ahmad Hegazy) / Repositories · GitHub (at github.com) | 19:06 |
| HEGAZY | I've checked the ideas repo but i am a bit lost, and I wanted a challenging task to learn something new, unfortunalty i don't have access to an FPGA to help in the bitstream mapping part. | 19:06 |
| HEGAZY | I was thinking of continuing the work on the sv-test repo (writing sv testcases from the lrm) in parrallel with a new challenging task for me, i need your input on this, what part of the project you need help most and where my experience can fit in the most? | 19:06 |
| HEGAZY | ** TL;DR ** | 19:06 |
| HEGAZY | * I am fascinated by the project and the amount of collaboration in it. | 19:07 |
| HEGAZY | * wanna join you in Gsoc, brief resume: https://drive.google.com/file/d/1BD8th3Zuzzcw29-JNe8uiaXAAjc-8fVz/view | 19:07 |
| tpb | Title: AhmadHegazyResume.pdf - Google Drive (at drive.google.com) | 19:07 |
| HEGAZY | * need help choosing a project to work on | 19:07 |
| HEGAZY | Thanks :D | 19:07 |
| ZirconiumX | Hi HEGAZY | 19:13 |
| ZirconiumX | You have quite the impressive resume | 19:14 |
| HEGAZY | thanks ZirconiumX, hope I can learn more contributing to this project | 19:16 |
| ZirconiumX | So, you don't need an FPGA to help with the bitstream tools | 19:18 |
| ZirconiumX | But then you don't need to work on the bitstream stuff either | 19:18 |
| HEGAZY | yeah i am a bit lost on where i can fit the most if you can help :D | 19:18 |
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| ZirconiumX | Hmm. Where in the flow would you like to work? This seems like an important question to ask. | 19:20 |
| sf-slack | <mgielda> hi Hegazy, I believe we will be able to help you choose a project. | 19:25 |
| sf-slack | <mgielda> happy to see the sv-tests work. this is mostly our doing and expanding it is welcome | 19:26 |
| sf-slack | <mgielda> there is an ongoing effort to improve sv support in open tooling and every little bit helps | 19:26 |
| HEGAZY | @ZirconiumX well the whole thing is just awesome, at first i was looking for some HDL challenge, like timing analysis, CDC, i haven't got my hands dirty in those topics, but i saw the project and the work on the tools, and i didn't know what should i focus on right now | 19:29 |
| sf-slack | <mgielda> rule #1 focus on what you like doing most | 19:30 |
| sf-slack | <mgielda> have you read this: https://symbiflow.github.io/summer-of-code ? | 19:32 |
| tpb | Title: SymbiFlow - the GCC of FPGAs (at symbiflow.github.io) | 19:32 |
| HEGAZY | Hi mgielda, thanks i will help as i could, yup 1st thing i read about a week ago, that's how i got here, i will reread it again now | 19:34 |
| sf-slack | <mgielda> I can see that you work in QA - do you think this is what you'd like to focus on, i.e. write more tests | 19:35 |
| sf-slack | <mgielda> or are you longing for a more development oriented tasks? ;) | 19:35 |
| sf-slack | <mgielda> how do you feel with Python? c++? | 19:36 |
| HEGAZY | yeah the QA work was my intern at mentor, honestly I am looking for a more challenging development oriented tasks, and i can help with the testcases too, | 19:38 |
| HEGAZY | yeah it would be good to work with python and C++, i started off with a little contribution PR #687 in sv-tests :D | 19:39 |
| sf-slack | <mgielda> we will take a look, I am sure the team will chat you up tomorrow to help you figure out how to best use your talents! | 19:40 |
| HEGAZY | I have a small question, is there any pure HDL related work other than sv-tests? | 19:40 |
| HEGAZY | Great thanks mgielda | 19:41 |
| ZirconiumX | Yosys could always use additional testing | 19:52 |
| sf-slack | <mgielda> there should be. just a matter of a well defined enough task you could take on | 19:54 |
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| clay_1 | litghost looks like the trick didnt work. top.bit.fasm gets overwritten when re-executing `make dram_test_64x1d_bit_v` | 20:31 |
| sf-slack | <acomodi> clay_1: try to replace the top.bit file with your bitstream instead. Fasm2bels works in a way that it dumps the fasm of the top.bit into top.bit.fasm, that is why it got overwritten | 20:36 |
| clay_1 | thanks! will try it | 20:36 |
| ZirconiumX | HEGAZY: to me there are a bunch of things to do in Yosys, but I don't know if you care much about that part of the flow | 20:41 |
| ZirconiumX | For example, I feel like much of Yosys could opportunistically work in parallel across module | 20:42 |
| HEGAZY | /join #yosys | 20:47 |
| HEGAZY | yup that was wrong | 20:47 |
| HEGAZY | ZirconiumX yeah that looks intersting, but right now i don't have a clue how it works from inside :D, i'll be reading its docs and clifford paper these next days to get a better understanding of the problem thanks | 20:49 |
| ZirconiumX | Claire. | 20:49 |
| ZirconiumX | Not Clifford. | 20:50 |
| clay_1 | I think that not all the documentation is updated on that matter yet ZirconiumX | 20:50 |
| HEGAZY | it said clifford on the paper http://www.clifford.at/yosys/files/yosys-austrochip2013.pdf , just saw the edit on the main site, sorry :D | 20:51 |
| ZirconiumX | True, but where you see "Clifford" use "Claire" | 20:51 |
| ZirconiumX | Mmm. Given that has a 2013 date, it's likely to be pretty heavily out of date I think | 20:52 |
| mithro | HEGAZY: Thank you for the pull request on sv-tests! | 20:52 |
| clay_1 | True, but I guess there will be a period of people making that misstake untill it settles. Also I am not sure what applies on referencing her work on official documents (since there might be conflict of names due to lack of update) | 20:54 |
| HEGAZY | mithro: you'r welcome, I hope it won't be the last | 20:54 |
| mithro | HEGAZY: If you have interest in sv-tests and related projects, there is plenty that could be done there as part of GSoC | 20:54 |
| ZirconiumX | clay_1: I'd definitely avoid deadnaming people even if the paper is published under an old name. | 20:55 |
| HEGAZY | can you illustrate more please | 20:55 |
| HEGAZY | or give an example | 20:56 |
| ZirconiumX | To whom are you replying? | 20:56 |
| HEGAZY | mithro | 20:56 |
| clay_1 | ZirconiumX I totally agree with that. I think that the best course of action is that if one plans to reference her and cant find a correct ref to directly come in contact with her and see if she can manually change that or something | 20:57 |
| mithro | I believe Claire has requested to be cited as "C. Wolf" if possible -- which covers both cases | 20:57 |
| ZirconiumX | Yeah. | 20:57 |
| clay_1 | @mithro clever ;) | 20:57 |
| mithro | HEGAZY: For example, we would love to work on a "system verilog feature detector" which is able to give you a list of the system verilog functionality a project is using and thus which tools will are more likely to be compatible with the project | 20:58 |
| HEGAZY | do you mean features like structs, classes, functions, conditions, loops etc or am i getting it wrong? | 21:01 |
| mithro | HEGAZY: yeah | 21:01 |
| mithro | HEGAZY: Adding more complex test cases to sv-tests which check things like simulation and synthesis actually work (rather than just parsing) would be another interesting project | 21:02 |
| mithro | HEGAZY: My main question for you is -- what are *you* excited about working on? | 21:02 |
| mithro | HEGAZY: being self motivated is an important part of being a GSoC student | 21:03 |
| mithro | bblr | 21:03 |
| ZirconiumX | I've considered entering GSoC, but I have pretty terrible focus... | 21:06 |
| HEGAZY | mithro: honstley i am a bit confused, too many options means more confusion for me :D | 21:07 |
| HEGAZY | and everything is exciting, i know that if i started on one thing my whole focus will be on it, but the problem is choosing that thing | 21:07 |
| ZirconiumX | Adding SV tests does seem like a useful thing | 21:08 |
| HEGAZY | anyway i'll read more on the projects you mentioned and comeback to you | 21:08 |
| HEGAZY | ZirconiumX: yeah i was thinking of it as a side contribution besides the main challenge | 21:09 |
| ZirconiumX | I wouldn't underestimate the complexity of it :P | 21:09 |
| HEGAZY | yeah i know i worked kinda full time on adding testcases but i wanna improve my experience in something new | 21:10 |
| HEGAZY | tbh i haven't considered software development seriously till i talked to you, it looks fun and challenging for me, and i think i do quite well on it | 21:12 |
| ZirconiumX | I actually came to hardware from software, rather than the other way round | 21:13 |
| ZirconiumX | And the software stack is what gets us to the bitstream at all :P | 21:15 |
| HEGAZY | my major is electronics so we are more focused on hardware, but i practiced with mircocontroller and stuff with C which is software dev. | 21:16 |
| HEGAZY | i didn't get the last message, software stack gets you to the bitstream how? | 21:16 |
| sf-slack | <aryap> hello again. are artix7 and zynq7 in the symbiflow-arch-defs repo the most advanced commercial-like architecture models available? | 21:22 |
| clay_1 | HEGAZY all the tools that do the bitstream reverse engineering are software so i think it makes sense in that way | 21:23 |
| clay_1 | @acomodi It worked, I mean now it doesnt get overwritten and I get an output. The wierd thing now is the output itself | 21:24 |
| clay_1 | when I try to synthesize the verilog file I get an error | 21:25 |
| HEGAZY | clay_1: it's more like the chicken or the egg | 21:25 |
| clay_1 | because signal led is defined both as an input and an output ` input [7:0] led, input rx, input tx, output [8:0] led` | 21:26 |
| clay_1 | HEGAZYI guess you could say so | 21:27 |
| ZirconiumX | HEGAZY: synthesis, place-and-route, bitstream assembly, bitstream programming; it's all software | 21:31 |
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