Wednesday, 2020-03-11

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litghostclay_1: You are using fasm2bels in a weird way.  fasm2bels is designed to convert the input FASM file into a top level verilog file that matches the original so that testbenches can run on the post-place&route output00:23
litghostclay_1: Some of the arguments to fasm2bels were specifically for the original bitstream, before you replaced it00:23
litghostclay_1: Solution is to invoke fasm2bels without arguments specific to the original design00:24
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sf-slack<aryap> hello01:57
sf-slack<aryap> is the symbiflow fork of vtr significantly different to upstream, currently?01:57
litghostaryap: Yes01:58
sf-slack<aryap> looks like there was a sync only a few days ago01:58
sf-slack<aryap> ok01:58
litghostaryap: We periodically bring in upstream changes, but there are significant downstream changes required for the flow01:58
sf-slack<aryap> is this mostly plumbing or significant work on QoR?01:59
sf-slack<aryap> i guess i can just run both01:59
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sf-slack<aryap> thanks :pray:02:01
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hackerfooaryap: Upstream VtR won't work with symbiflow-arch-defs. We are working to upstream our changes, but it takes time.02:12
sf-slack<aryap> aha, great02:16
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mithroaryap: litghost has been working hard to get a bunch of stuff upstream lately02:44
sf-slack<aryap> nice work :clap:02:45
sf-slack<aryap> should i be able to run any of the titan benchmarks on the xc7a50t arch from symbiflow-arch-defs?02:59
sf-slack<aryap> i get this a lot: ```Error 1: [blah]/symbiflow-vtr/libs/libvtrutil/src/vtr_util.cpp:190 Failed to convert string '{iopath_A1_O5}' to float```02:59
mithroaryap: That means you have broken the symbiflow architecture generation -- it hasn't patched in the timing information03:05
mithroaryap: Nobody has gotten the titan benchmarks (**not** to be confused with a benchmark containing opentitan) running on symbiflow architectures -- but that would be an excellent project03:06
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HEGAZYHi all, again, remember me?17:10
HEGAZYso we talked yesterday about the Gsoc project for #symbiflow , I've thought it through and I am intersted in "system verilog feature detector" you told me about,17:10
HEGAZYI have an initial plan on how the work is going to go, but first i have couple of questions I need to discuss with you :D17:10
HEGAZYmithro said "For example, we would love to work on a "system verilog feature detector" which is able to give you a list of the system verilog functionality a project is using and thus which tools will are more likely to be compatible with the project"17:11
HEGAZY- I see that the third party tools takes .sv files directly, so  are the tools already support some kinda of verilog structure format that i should return as a result? or is this for future integration?17:11
HEGAZY- why not use an existing parser for sv, I mean all the third party tools like yosys parse the code 1st and their parser opensource that can be ported here right?17:11
ZirconiumXHEGAZY: essentially "because nobody's done it yet".17:12
ZirconiumXVHDL support is more or less third-party17:13
HEGAZYdone what exactly? there is this project for example https://github.com/ben-marshall/verilog-parser17:13
tpbTitle: GitHub - ben-marshall/verilog-parser: A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard. (at github.com)17:13
ZirconiumXThat's Verilog not SystemVerilog17:13
ZirconiumXYosys has a native Verilog parser17:14
ZirconiumXWith some SV extensions17:14
HEGAZYgreat, didn't know that nobody's done it yet :D17:16
ZirconiumXThere's talk of trying to integrate the Google SV parser17:19
ZirconiumXBut it would essentially need a build system transplant17:19
ZirconiumXLike, I'm pretty sure ghdlsynth couldn't be mainlined because it drags in an Ada codebase17:24
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mithroHEGAZY: If you already had good system verilog support you wouldn't need the system verilog feature tester17:54
mithroHEGAZY: did you see the sv-test project?17:54
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HEGAZYmithro: yup saw it, i was wondering about the existance of such a project not how effective it is, i got you now17:58
mithroHEGAZY: SystemVerilog and Verilog are about as similar as C++ and C17:59
mithroHEGAZY: If you look at https://symbiflow.github.io/sv-tests/ you'll see lots of red17:59
tpbTitle: SystemVerilog Report (at symbiflow.github.io)17:59
HEGAZYdalance sv-parser is doing well right?18:05
mithroHEGAZY: yeah - but that is just a parser and isn't integrated into tools like Yosys or Verilator18:10
mithrolitghost: Does this look okay? https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master -- It's missing zynq as that hasn't finished yet18:10
tpbTitle: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com)18:10
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sf-slack<aryap> uh oh. i ran the instructions to generate the arch from HEAD. unmodified21:34
sf-slack<aryap> ok interesting21:34
sf-slack<aryap> oh i see. i have to use the arch.timing.xml file21:37
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litghostmithro: Diff looks good23:07

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