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litghost | clay_1: You are using fasm2bels in a weird way. fasm2bels is designed to convert the input FASM file into a top level verilog file that matches the original so that testbenches can run on the post-place&route output | 00:23 |
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litghost | clay_1: Some of the arguments to fasm2bels were specifically for the original bitstream, before you replaced it | 00:23 |
litghost | clay_1: Solution is to invoke fasm2bels without arguments specific to the original design | 00:24 |
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sf-slack | <aryap> hello | 01:57 |
sf-slack | <aryap> is the symbiflow fork of vtr significantly different to upstream, currently? | 01:57 |
litghost | aryap: Yes | 01:58 |
sf-slack | <aryap> looks like there was a sync only a few days ago | 01:58 |
sf-slack | <aryap> ok | 01:58 |
litghost | aryap: We periodically bring in upstream changes, but there are significant downstream changes required for the flow | 01:58 |
sf-slack | <aryap> is this mostly plumbing or significant work on QoR? | 01:59 |
sf-slack | <aryap> i guess i can just run both | 01:59 |
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sf-slack | <aryap> thanks :pray: | 02:01 |
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hackerfoo | aryap: Upstream VtR won't work with symbiflow-arch-defs. We are working to upstream our changes, but it takes time. | 02:12 |
sf-slack | <aryap> aha, great | 02:16 |
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mithro | aryap: litghost has been working hard to get a bunch of stuff upstream lately | 02:44 |
sf-slack | <aryap> nice work :clap: | 02:45 |
sf-slack | <aryap> should i be able to run any of the titan benchmarks on the xc7a50t arch from symbiflow-arch-defs? | 02:59 |
sf-slack | <aryap> i get this a lot: ```Error 1: [blah]/symbiflow-vtr/libs/libvtrutil/src/vtr_util.cpp:190 Failed to convert string '{iopath_A1_O5}' to float``` | 02:59 |
mithro | aryap: That means you have broken the symbiflow architecture generation -- it hasn't patched in the timing information | 03:05 |
mithro | aryap: Nobody has gotten the titan benchmarks (**not** to be confused with a benchmark containing opentitan) running on symbiflow architectures -- but that would be an excellent project | 03:06 |
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HEGAZY | Hi all, again, remember me? | 17:10 |
HEGAZY | so we talked yesterday about the Gsoc project for #symbiflow , I've thought it through and I am intersted in "system verilog feature detector" you told me about, | 17:10 |
HEGAZY | I have an initial plan on how the work is going to go, but first i have couple of questions I need to discuss with you :D | 17:10 |
HEGAZY | mithro said "For example, we would love to work on a "system verilog feature detector" which is able to give you a list of the system verilog functionality a project is using and thus which tools will are more likely to be compatible with the project" | 17:11 |
HEGAZY | - I see that the third party tools takes .sv files directly, so are the tools already support some kinda of verilog structure format that i should return as a result? or is this for future integration? | 17:11 |
HEGAZY | - why not use an existing parser for sv, I mean all the third party tools like yosys parse the code 1st and their parser opensource that can be ported here right? | 17:11 |
ZirconiumX | HEGAZY: essentially "because nobody's done it yet". | 17:12 |
ZirconiumX | VHDL support is more or less third-party | 17:13 |
HEGAZY | done what exactly? there is this project for example https://github.com/ben-marshall/verilog-parser | 17:13 |
tpb | Title: GitHub - ben-marshall/verilog-parser: A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard. (at github.com) | 17:13 |
ZirconiumX | That's Verilog not SystemVerilog | 17:13 |
ZirconiumX | Yosys has a native Verilog parser | 17:14 |
ZirconiumX | With some SV extensions | 17:14 |
HEGAZY | great, didn't know that nobody's done it yet :D | 17:16 |
ZirconiumX | There's talk of trying to integrate the Google SV parser | 17:19 |
ZirconiumX | But it would essentially need a build system transplant | 17:19 |
ZirconiumX | Like, I'm pretty sure ghdlsynth couldn't be mainlined because it drags in an Ada codebase | 17:24 |
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mithro | HEGAZY: If you already had good system verilog support you wouldn't need the system verilog feature tester | 17:54 |
mithro | HEGAZY: did you see the sv-test project? | 17:54 |
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HEGAZY | mithro: yup saw it, i was wondering about the existance of such a project not how effective it is, i got you now | 17:58 |
mithro | HEGAZY: SystemVerilog and Verilog are about as similar as C++ and C | 17:59 |
mithro | HEGAZY: If you look at https://symbiflow.github.io/sv-tests/ you'll see lots of red | 17:59 |
tpb | Title: SystemVerilog Report (at symbiflow.github.io) | 17:59 |
HEGAZY | dalance sv-parser is doing well right? | 18:05 |
mithro | HEGAZY: yeah - but that is just a parser and isn't integrated into tools like Yosys or Verilator | 18:10 |
mithro | litghost: Does this look okay? https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master -- It's missing zynq as that hasn't finished yet | 18:10 |
tpb | Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com) | 18:10 |
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sf-slack | <aryap> uh oh. i ran the instructions to generate the arch from HEAD. unmodified | 21:34 |
sf-slack | <aryap> ok interesting | 21:34 |
sf-slack | <aryap> oh i see. i have to use the arch.timing.xml file | 21:37 |
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litghost | mithro: Diff looks good | 23:07 |
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