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| Xiretza | _florent_: do you know where you got the numbers for the ECP5 PLL VCO frequency range (https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/clock.py#L510)? they don't align with prjtrellis, but I can't find any source of truth (TN1263 doesn't mention it as far as I can tell). | 13:32 |
|---|---|---|
| tpb | Title: litex/clock.py at master · enjoy-digital/litex · GitHub (at github.com) | 13:32 |
| daveshah | Xiretza: the datasheet has them, iirc | 13:33 |
| daveshah | The numbers in LiteX definitely don't look right, I also know from experimentation with Diamond that the range is 400-800MHz | 13:34 |
| Xiretza | daveshah: oh, you're right, the ECP5 family datasheet has timing information, and f_vco is indeed 400-800 MHz. | 13:36 |
| Xiretza | that's unfortunate, it means usb3_pipe needs at least two PLLs for its 100 -> (125, 200) clocks | 13:37 |
| _florent_ | Xiretza: thanks for the catching this, i'll update | 13:49 |
| Xiretza | _florent_: I sent a PR | 13:50 |
| _florent_ | ah ok thanks! | 13:50 |
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| -_whitenotifier-3- [symbiflow-arch-defs] sjha2048 opened issue #1331: upgrading to ubuntu 18.04 - https://git.io/JvEzg | 19:00 | |
| -_whitenotifier-3- [prjxray-dev-env] sjha2048 opened issue #1: upgrading to ubuntu 18.04 - https://git.io/JvEzr | 19:02 | |
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