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| mithro | litghost: New database push at https://github.com/mithro/prjxray-db/compare/SymbiFlow:master...master | 06:05 |
|---|---|---|
| tpb | Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com) | 06:05 |
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| jayanthj737 | Hello Sir, Really Interested and looking forward towards working on Open Source PROJECT handles by Symbiflow. I would be pleased to know more about it and also to gather enough skills for the sameThanking You.Jayanth Jayadevan | 10:41 |
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| ZirconiumX | jayanthj737: have you ever used Verilog? | 11:33 |
| ZirconiumX | I'm not mithro, but I can offer some ideas of my own | 11:34 |
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| jayanthj737 | No thats my only concern. But have programmed PIC ICs | 11:38 |
| ZirconiumX | (for the record I am not a sir) | 11:38 |
| ZirconiumX | Right. You don't *need* to know Verilog but if you're going to apply for Symbiflow you should read up on FPGA architecture. | 11:38 |
| ZirconiumX | PICs are nowhere close to FPGAs; the programming model is fundamentally different | 11:39 |
| ZirconiumX | jayanthj737: ^ | 11:43 |
| jayanthj737 | Sure thing. | 11:46 |
| ZirconiumX | The talk "Everything Wrong With FPGAs" by Ben Widawsky gives a good overview of FPGA architecture, even if they're not the main focus of the talk | 11:47 |
| ZirconiumX | It's also not *that* long | 11:48 |
| ZirconiumX | jayanthj737: a personal idea for GSoC I've had is in how Yosys maps to FPGA LUTs | 11:51 |
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| abeljj[m] | a personal idea for GSoC I've had is in how Yosys maps to FPGA LUTs | 12:08 |
| abeljj[m] | ZirconiumX , isn't yosys a synthesis suite for vlsi? | 12:08 |
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| ZirconiumX | It *can* target VLSI, but much of the present work goes into FPGAs as a back-end | 12:09 |
| ZirconiumX | Lattice iCE40 and ECP5 FPGAs both have mature synthesis targets, abeljj[m] | 12:10 |
| ZirconiumX | Xilinx work is progressing, although I'm unfamiliar with the place-and-route side of things | 12:11 |
| ZirconiumX | And I've been trying to target Intel chips | 12:14 |
| abeljj[m] | I have used yosys with qflow, where the target technology were openly available. But with fpga and intel chips is it a try and error method? | 12:16 |
| ZirconiumX | You're going to have to be more specific: there is no trial-and-error needed for synthesis | 12:18 |
| abeljj[m] | Since the architecture is closed, how is synthesis done? | 12:18 |
| ZirconiumX | Either the FPGA bitstream gets reversed or you can use Quartus to perform place-and-route | 12:19 |
| ZirconiumX | The first two are how iCE40 and ECP5 work, the latter is my current target, and what Xilinx can do too | 12:20 |
| ZirconiumX | (but for Vivado/ISE) | 12:20 |
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| yusef | "Support Xilinx XC9500XL CPLD series" so, what do we have to do in this? | 15:11 |
| ZirconiumX | yusef: reverse engineer the bitstream format, mostly. | 15:16 |
| ZirconiumX | Which requires using ISE and that won't be very fun :P | 15:25 |
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| mithro | Did we ever write that RAM in bitstream patching for Xilinx Series 7? | 16:32 |
| sf-slack | <kgugala> I don't think so | 16:33 |
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| Jihad | Hello everybody, what is the topics should I study? | 22:39 |
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