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| mithro | daveshah: I generated a database with your DSP changes | 02:10 |
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| -_whitenotifier-3- [ideas] Harvie opened issue #39: Support for cheapest FPGAs on the market - https://git.io/Jvm5Q | 02:18 | |
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| mithro | https://github.com/YosysHQ/yosys/pull/1657/files | 03:33 |
| tpb | Title: synth_xilinx: add -dsp-multonly by daveshah1 · Pull Request #1657 · YosysHQ/yosys · GitHub (at github.com) | 03:33 |
| mithro | daveshah: It seems like support for that would be pretty easy to add in vpr | 03:34 |
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| -_whitenotifier-3- [prjxray] acomodi opened issue #1214: Bottleneck in 072 and 074 fuzzers - https://git.io/JvYIM | 12:27 | |
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| sf-slack1 | <acomodi> litghost: given that most of the tiles are actually equal, wouldn't it be ok to just dump a smaller subset of the whole device in fuzzer 074? | 14:36 |
| sf-slack1 | <acomodi> We could for instance use an ROI that includes 1 or 2 clock regions only, this way we can include all tiles that share the name, but have some discrepancies with the wires. (e.g. https://github.com/SymbiFlow/prjxray/blob/3f0804a417666ab76251c6469c9cc69801eb501a/fuzzers/074-dump_all/reduce_tile_types.py#L135-L136) | 14:38 |
| tpb | Title: prjxray/reduce_tile_types.py at 3f0804a417666ab76251c6469c9cc69801eb501a · SymbiFlow/prjxray · GitHub (at github.com) | 14:38 |
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| mithro | http://yibolin.com/publications/papers/FPGA_ASPDAC2020_Alawieh.pdf | 17:47 |
| mithro | "High-Definition Routing Congestion Prediction for Large-Scale FPGAs" | 17:48 |
| mithro | litghost: ^ | 17:48 |
| mithro | daveshah: You might also be interested in the above... | 17:48 |
| mithro | daveshah: I'm trying to get that group to release the source code for their work | 17:50 |
| daveshah | That would be interesting | 17:50 |
| mithro | daveshah: Apparently the top student went to Xilinx to implement the same thing in vivado.... | 17:53 |
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| mithro | litghost: 100 billion! | 19:09 |
| litghost | mithro: Yep :) | 19:09 |
| mithro | litghost: Also -> https://github.com/martinmoene/string-view-lite | 19:10 |
| tpb | Title: GitHub - martinmoene/string-view-lite: string_view lite - A C++17-like string_view for C++98, C++11 and later in a single-file header-only library (at github.com) | 19:10 |
| mithro | litghost: Dunno if it's any good or useful... | 19:10 |
| litghost | mithro: This wasn't a string-view case | 19:11 |
| litghost | mithro: It was a simple case of forgetting to hold a reference vs value | 19:11 |
| mithro | litghost: the two things were unrelated | 19:30 |
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| litghost | k | 19:32 |
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| -_whitenotifier-3- [vtr-verilog-to-routing] acomodi opened issue #367: VTR does not allow constrained clocks with dots in the name - https://git.io/JvY0l | 19:34 | |
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