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| mangelis | hi | 08:30 |
|---|---|---|
| mangelis | is there some way to debug (other than running the actual bitstream on device) what yosys/nextpnr generates? | 08:31 |
| mangelis | i have a case where things work weirdly on device, but seem to be okay when simulated on verilator | 08:31 |
| sf-slack1 | <mkurc> What FPGA are you targeting ? | 08:35 |
| mangelis | ECP5 | 08:44 |
| sf-slack1 | <mkurc> For ECP5 I can't tell. But for XC7 we have a tool called fasm2bels that can basically decode a bitstream to verilog. | 08:49 |
| daveshah | No, there isn't anything like this for ECP5 | 09:06 |
| mangelis | i wonder write_verilog command would work on yosys | 09:30 |
| daveshah | Yes, that tests the Yosys side at least | 09:31 |
| sf-slack1 | <mkurc> Provided that you have proper simulation models for cells that are used by the synthesized design. | 09:33 |
| sf-slack1 | <mkurc> Most of them should be part of Yosys cells_sim.v library file for ECP5. | 09:33 |
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| mangelis | ah does write_verilog also output code that implements the luts too? | 10:32 |
| ZirconiumX | If you run it after synth_ecp5, yes | 10:34 |
| mangelis | are there any good netlist viewers for linux? | 10:39 |
| ZirconiumX | Depends what you mean by netlist viewing. You can use `show` to dump a massive GraphViz plot | 10:39 |
| abeljj[m] | Check out opencircuitdesign by TimEdwards | 10:40 |
| abeljj[m] | mangelis: | 10:40 |
| abeljj[m] | * | 10:40 |
| mangelis | just wondering about those write_ commands that write netlists that what should be used to view those files | 10:40 |
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| mangelis | okay, since write_verilog didn't show anything suspicious, i found the issue was actually in the other connected device. thanks for the tips! | 20:30 |
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