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| mithro | Anyone ever used dinotrace? https://www.veripool.org/wiki/dinotrace | 17:14 |
|---|---|---|
| tpb | Title: Intro - Dinotrace - Veripool (at www.veripool.org) | 17:14 |
| hackerfoo | A REPL for Verilog would be useful if it wasn't so unwieldy. I just want to pole at a design in different places and see the output. | 17:32 |
| hackerfoo | Or maybe a higher level waveform analyzer that is more like a debugger. | 17:34 |
| hackerfoo | litghost: Is it expected to not find any routes for the CCIO_CLK_IN segment type during lookahead? | 18:01 |
| litghost | For the basys3 graph? ya that's expected, because the CCIO_CLK_IN is only present in ROI-less graphs | 18:02 |
| hackerfoo | Okay. | 18:02 |
| litghost | The 4 new segment types in https://github.com/SymbiFlow/symbiflow-arch-defs/commit/dd50d9c276d1c210014b157fa62cbb4679522573#diff-0d0df02682da654e71b63e89d7109083R74 are all only really present on ROI-less graphs | 18:03 |
| tpb | Title: Assorted hacks to try to get clock network working. · SymbiFlow/symbiflow-arch-defs@dd50d9c · GitHub (at github.com) | 18:03 |
| hackerfoo | https://www.reddit.com/r/FPGA/comments/diow8k/hdl_checker/ | 19:36 |
| tpb | Title: HDL Checker : FPGA (at www.reddit.com) | 19:36 |
| hackerfoo | litghost: Is it expected that BYP_L and FAN_L segments can't reach IMUX connection boxes? | 19:45 |
| litghost | you can check with vivado | 19:45 |
| mankeli | i've used verilator for prototyping | 19:48 |
| mankeli | but it seems that the syntax differs between it and vivado :/ | 19:49 |
| hackerfoo | litghost: I have no idea how to check that in Vivado. | 19:53 |
| litghost | Did you find a BYP_L wire? | 19:53 |
| litghost | e.g. "select_objects [get_wires *BYP_L*]" | 19:53 |
| hackerfoo | Okay, those seem to be really short wires between two pips. | 19:59 |
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