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| mithro | maybe someone should run https://github.com/maximuska/depslint on symbiflow? | 02:37 |
|---|---|---|
| tpb | Title: GitHub - maximuska/depslint: A tool for dependencies validation for ninja build system using strace to detect the real dependencies (at github.com) | 02:37 |
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| rajesh-s | hello | 13:04 |
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| hackerfoo | hi rajesh-s | 16:58 |
| hackerfoo | Ah, they left. | 16:59 |
| mithro | daveshah: https://github.com/enjoy-digital/usb3_pipe/issues/12#issuecomment-543765455 | 17:02 |
| tpb | Title: ECP5: Validate SerDes at 5Gbps · Issue #12 · enjoy-digital/usb3_pipe · GitHub (at github.com) | 17:02 |
| daveshah | mithro: ack, will investigate over the weekend | 17:15 |
| mithro | daveshah: _florent_ just said "The timings have been improved and the Host now receives correctly the TSEQ/TS1 from the Versa ECP5. I still need to look at the RX path, but we should not be far from being able to use the Versa ECP5 for the dev." | 18:06 |
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| _florent_ | daveshah, mithro: i was expecting these timing violations, this was a first report without any optimizations. TX is now fine, RX is not far but i just spend a few minutes looking at it, i need to spend more time. The timings issue seems to be around the 8b10b decoder (which is done in the fabric), i'll probably need to do some optimizations | 20:12 |
| daveshah | Is there a reason you aren't using the hard 8b10b? | 20:13 |
| mithro | _florent_: Yeah - I was just pointing daveshah to someone doing something cool with the ecp5 | 20:13 |
| _florent_ | daveshah: yes, i just want to use the serdes as simple serializer/deserializer (as we are doing with others FPGAs), and this is also useful to generate LFPS | 20:16 |
| _florent_ | daveshah: but if it's really causing timing issues, i'll probably switch to the hard ones | 20:16 |
| daveshah | _florent_: ack, I think there is some OOB functionality that could be used for LFPS | 20:16 |
| mankeli | any idea when that ECP5 tinyfpga is coming and how much it will cost? | 20:17 |
| mankeli | since it has serdes, it should be capable of hdmi right? | 20:18 |
| daveshah | The SERDES isn't actually a very good match for HDMI | 20:19 |
| daveshah | Wrong signalling level | 20:19 |
| daveshah | If you only need 720p60 or 1080p30, regular ECP5 IO pins are actually a better choice | 20:19 |
| mankeli | no? I have used serdes (although friend did the ip) on zynq7 for hdmi | 20:20 |
| daveshah | Ah, paths are crossed here | 20:21 |
| daveshah | "serdes" in Xilinx sense is presumably referring to IO SERDES primitives, ie still regular IO pins | 20:21 |
| mankeli | ah | 20:21 |
| daveshah | There's also the high speed transceiver for PCIe, USB3, etc (GTX/GTH/etc in Xilinx) | 20:22 |
| _florent_ | daveshah: btw, i added SCI support to have more control on the serdes parameters | 20:23 |
| daveshah | Very nice | 20:23 |
| daveshah | That should make tuning easier | 20:23 |
| mankeli | it's the OSERDESE2 primitive that does the diff serial output | 20:24 |
| daveshah | So the ECP5 doesn't have an exact equivalent to that | 20:27 |
| daveshah | But it has ODDRX2F which is the same as an OSERDESE2 in 4:1 DDR mode | 20:27 |
| daveshah | Unfortunately no 10:1 or 8:1 mode | 20:27 |
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| mankeli | there's some document describing hdmi on ECP3 using "CML SERDES", is that something different than what the ECP5 has? | 20:38 |
| daveshah | As far as I know, the only options for HDMI on ECP5 are the transceivers (Lattice call them SERDES, GTX in Xilinx world) with a level shifter; or regular IO pins and a 4:1 gearbox (SERDES in Xilinx world) | 20:39 |
| daveshah | But the latter option can't do 1080p60 | 20:39 |
| daveshah | That app note seems to be using a level shifter | 20:40 |
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