Saturday, 2021-05-08

*** tpb has joined #litex00:00
*** pftbest has quit IRC00:02
*** Degi_ has joined #litex00:06
*** Degi has quit IRC00:07
*** Degi_ is now known as Degi00:07
*** feldim2425 has quit IRC00:34
*** feldim2425_ has joined #litex00:34
*** feldim2425_ is now known as feldim242500:34
*** Emantor has quit IRC01:20
*** Emantor has joined #litex01:23
*** TMM has quit IRC04:32
*** TMM has joined #litex04:32
*** Bertl is now known as Bertl_zZ04:36
*** pftbest has joined #litex07:00
*** kgugala_ has joined #litex07:23
*** kgugala has quit IRC07:27
*** pftbest has quit IRC07:32
*** kgugala has joined #litex08:09
*** kgugala_ has quit IRC08:12
*** pftbest has joined #litex08:15
nickoeohh,... mmm, if I use cdc.source.ready to incremente the addr  it work! ... I am not sure why that is... mmm08:46
nickoezyp: https://github.com/nickoe/litex-boards/commit/b526e5cd394aabaaf2d7497128d035bafdf6e94a#diff-20ac2baa37a4011312f33c4b6bc95738a86519505d8706cc8b3b381f3949a89cR17608:57
zypbecause ready indicates when the receiver is ready for a new address09:00
zypso incrementing the address only when it's ready for a new address makes sense09:00
nickoeah, right. I am still not very intuitive to the signal names and directions :S09:01
nickoeyes! I understand that, but I clearly mess it up sometimes :D09:01
nickoeI think my thinking was that, if the sink is ready to receive,... but that signal is the ready signal in the middle of the chain instead of the end where I want to control it from09:05
nickoeif that makes any sense at all09:05
zypeach element in the pipeline only needs to consider the flow control signals of the elements it's directly adjacent to09:06
zypthe bottleneck in your pipeline should be the DAC, since it's running at a fixed rate09:07
nickoeyes09:07
zypthe DAC will be fed by the DMA as fast as the DAC is ready to receive new data09:07
zypand then the DMA will be fed with new addrs as fast as it is ready to receive more addrs09:08
zypthey will then naturally end up averaging the same rate, but since the DMA works in bursts, it'll also be ready for new addrs in bursts, not at an even rate09:09
zypand due to the flow control signals it should just work out09:09
nickoeso is this correct signals used in the If? https://github.com/nickoe/litex-boards/blob/bdf9dd30672499fab837bf480927a7b6d6ace6bb/litex_boards/targets/mars_ax3_custom.py#L175-L17909:10
zypmaybe, I haven't studied the full picture of your application :)09:10
nickoeI mean this is the whole chain https://github.com/nickoe/litex-boards/blob/bdf9dd30672499fab837bf480927a7b6d6ace6bb/litex_boards/targets/mars_ax3_custom.py#L114-L12809:11
nickoedma -> cdc -> dac09:11
* nickoe really needs to clean it up a bit now09:13
zypyou should probably not do anything about cdc.source there, cdc.source is in the other clock domain09:13
zypif I'm reading it right09:13
nickoeWith that code it appears to work good, as https://i.snipboard.io/GHJYlm.jpg, ...09:17
nickoeand now when I remove it it ALSO works :S odd09:17
nickoeBut finally it looks like I wanted it to two weeks ago. zyp Thank you very much for your help! I owe you a keg of beer.09:18
nickoezyp: Can I detect in a Module if this is a simulation?09:26
nickoeah, never mind, I don't need to09:27
nickoeI just have the signalsin the simulation _io09:27
*** kgugala_ has joined #litex10:11
*** kgugala has quit IRC10:14
nickoemmm, right now the analyzer does not dump a lot over jtag10:35
nickoeIt just does: [uploading]...       [>                    ] 0%         [writing to dump.vcd]...10:36
nickoecalling litescope_cli without args do seem to dump stuff10:40
*** pftbest has quit IRC11:47
nickoezyp: For soe reason it just appears to be happy to consume addresses a bit too much https://i.snipboard.io/T8KYa2.jpg11:48
nickoeI wonder why the dma.sink.ready has that strage pattern with one high cycle, one low, then a couple high.11:50
nickoeThat is on hardware. The sim looks good.11:52
*** pftbest has joined #litex11:57
*** Bertl_zZ is now known as Bertl13:27
*** Bertl is now known as Bertl_oO13:34
nickoeit is a bit hard to compare the traces https://i.snipboard.io/9HRmpj.jpg14:00
nickoeat littele bit more https://i.snipboard.io/geh8WT.jpg14:03
nickoeSo on the target it appears that the dma.sink.ready signal is flopping a bit onre14:04
nickoea bit more14:04
*** TMM has quit IRC14:04
*** TMM has joined #litex14:04
nickoerestulting in the address being updated14:04
*** lfforth has joined #litex15:47
*** lfforth has quit IRC15:50
*** chgavilana has joined #litex16:42
chgavilanahi, over linux, gpioset work for all here? for me just gpio-hammer work for gpio on linux-on-litex-vexriscv using GPIOOut16:44
*** pftbest has quit IRC16:56
*** pftbest has joined #litex16:58
*** pftbest has quit IRC17:02
*** pftbest has joined #litex17:23
*** pftbest has quit IRC17:26
*** pftbest has joined #litex17:27
*** pftbest has quit IRC17:29
*** pftbest has joined #litex17:30
*** pftbest has quit IRC17:51
*** pftbest has joined #litex17:52
*** pftbest has quit IRC17:52
*** pftbest has joined #litex19:33
*** pftbest has quit IRC19:36
*** pftbest has joined #litex19:36
*** pftbest has quit IRC19:55
*** pftbest has joined #litex19:56
*** pftbest has quit IRC20:56
*** pftbest has joined #litex20:57
nickoechgavilana: What are you talking about?21:18
*** pftbest has quit IRC21:32
*** pftbest has joined #litex21:32
chgavilanain linux_on_litex_vexriscv project, what command do you use to control the gpios ?, is that sysfs is no longer in kernel 5+21:40
nickoeDunno, I am not really using the linux stuff in litex at the moment, but can't you just enable sysfs, evne though it is 5+?21:44
nickoeI am not sure what the replacement for sysfs is.21:45
*** lf has quit IRC23:09
*** lf has joined #litex23:10
*** peepsalot has quit IRC23:21
*** peepsalot has joined #litex23:21

Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!