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| nickoe | mmm, is this a bad idea to try to make the clock of a module slower? self.comb += ClockSignal().eq(clock_domain.clk) | 09:33 |
|---|---|---|
| nickoe | Vsim just appears to never complete. | 09:33 |
| nickoe | _florent_: Is there or was there a bug in litedram that could cause the LiteDRAMDMAReader to act differently in simulation and hardware? https://i.snipboard.io/geh8WT.jpg I am talking about the mydma_dma_sink_sink_ready signal. In the simulation it ready'es a lot to fill its fifo, but on hardware it does not and it will have those odd ready signals multiple clock cylces with a low cycle. | 09:59 |
| nickoe | I am currently on litedram 080948d49c0cfe3fa8e10dcea1ae123bbe3949ac which is a bit old. I have not tested my design on latest of everything yet. | 10:01 |
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| mikeK_de1soc | Hi Nickoe: Can I ask you a questions about litex? | 11:54 |
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| nickoe | mikeK_de1soc: you can try, but I am no expert | 12:07 |
| mikeK_de1soc | Thanks. Like I said I am still learning, IS there an example of using the PWM function that Florent has in some of his example code? | 12:09 |
| mikeK_de1soc | So for example I am looking through the Litex-boards examples, and I found something under LEDs but it looks like you can only use the PWM through the CSR's from the Risc-V cpu? | 12:10 |
| mikeK_de1soc | The question is not confusing I hope.. | 12:11 |
| mikeK_de1soc | Bascally How can I access the pins in Litex-Boards? | 12:11 |
| mikeK_de1soc | Maybe that's too loaded of a question... | 12:12 |
| mikeK_de1soc | Sorry. | 12:12 |
| mikeK_de1soc | Lets TRy this simple Question How Do I send a Link to a Line of the Code, From Github for example? | 12:27 |
| mikeK_de1soc | https://github.com/enjoy-digital/litex/blob/9bec0ce7a28afb498c7b7eb79943c270225c061a/litex/soc/cores/led.py | 12:28 |
| mikeK_de1soc | Here's the Code I am working with... I just need to add the PPM modulation Here instead of the PWM?? (This is my Ultimate Goal, To send PPM signals to an RC controller instead of PWM signals) | 12:30 |
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| nickoe | mikeK_de1soc: You can clik the line number or multiple to get a direct link range that is highlighted | 13:05 |
| mikeK_de1soc | OK thanks! | 13:06 |
| nickoe | that CSRStorage is available as a register you can write or read to from the cpu | 13:07 |
| nickoe | litex_cli --regs | grep led | 13:07 |
| nickoe | 0x82005800 : 0x00000000 leds_out | 13:07 |
| nickoe | in my design | 13:07 |
| mikeK_de1soc | Ok thanks... IS there a Wiki example or documented somewhere? | 13:08 |
| nickoe | and that add_pwm function is just exactly that, an example on how to use the PWM() module | 13:09 |
| mikeK_de1soc | Right now my Linux-on-litex-vexriscv build envrioment is broken.. :( | 13:10 |
| nickoe | I have mostly been using the bare metal cpu thing, not the linux one | 13:10 |
| mikeK_de1soc | ah ok.. | 13:10 |
| nickoe | What hardware do you have? | 13:11 |
| mikeK_de1soc | Altera... DE10NAno and the DE1Soc | 13:11 |
| mikeK_de1soc | hence in the name... :) | 13:11 |
| nickoe | ok | 13:11 |
| mikeK_de1soc | Do you have an example of a Bare metal CPU? | 13:12 |
| mikeK_de1soc | A wiki if you will?? | 13:12 |
| nickoe | I think you can add some other CSRStorage things to attach to the args of add_pwm and you can control the pwm from the cpu | 13:12 |
| mikeK_de1soc | I am driking from the firehose here.. :) | 13:12 |
| nickoe | essentially the same as you do for linux, just that you don't run linux | 13:13 |
| nickoe | https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU | 13:13 |
| mikeK_de1soc | Sweet thanks!! | 13:14 |
| nickoe | I build the demo.bin with: python ../../../litex/litex/soc/software/demo/demo.py --build-path=build/sim | 13:14 |
| nickoe | and that builds a main.c somewhre in the demo path that you can modify | 13:14 |
| nickoe | the demo vil write to the led register directly here, https://github.com/nickoe/litex/blob/1540aeaa701e220ce42038acd4ee8c8c7fe03c5a/litex/soc/software/demo/main.c#L108-L136 | 13:16 |
| mikeK_de1soc | Oh wow... | 13:16 |
| mikeK_de1soc | Ok, so is this Riscv based?? | 13:16 |
| nickoe | yes | 13:17 |
| mikeK_de1soc | ok.... | 13:17 |
| mikeK_de1soc | so you still need the Linux-on-litex-vexriscv | 13:17 |
| nickoe | So if you want to implement the PPM protocol, I guess you want to create your own simple PPM module and give it some registers you can control from sw | 13:17 |
| nickoe | no, I am not using linux-on-llitex-vexriscv | 13:18 |
| nickoe | Just using the example in litex-boards directly | 13:18 |
| mikeK_de1soc | oh ok... | 13:18 |
| mikeK_de1soc | that's exactly what I am doing, I took the PWM code, then I am changing it to the PPM, in Verilog. (well python to verilog) | 13:20 |
| mikeK_de1soc | where I get a little confused is where the Gateware stops and the software starts.. | 13:20 |
| mikeK_de1soc | the links you sent is a great start... more reading!! :) | 13:21 |
| nickoe | well, the python is essentially gateware | 13:21 |
| nickoe | as it generates verilog | 13:21 |
| nickoe | if you add --csr-csv=csr.csv when building your target, you can see what registers you can acccess | 13:22 |
| nickoe | or, I call them registers, but they are the CSRStorage things | 13:22 |
| mikeK_de1soc | AH ok... | 13:22 |
| nickoe | That can be wired up to signals in the gateware but are addressable from the CPU | 13:23 |
| nickoe | or that etherbone stuff | 13:23 |
| nickoe | https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC | 13:23 |
| mikeK_de1soc | Yes, I remember now. still learning, The only down side right now with the Terasic boards, is that the Ethernet is connected to the CPU side on the ARM processor PART in the FPGA IC. | 13:25 |
| nickoe | Is it possible to use that CPU in the litex soc project or is that not supported? | 13:26 |
| mikeK_de1soc | well.. it's complicated... No from my limited understanding.. | 13:27 |
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| mikeK_de1soc | it's not supported.. So long story, within the Quartus SOC builder you create a SOC system with the Canned Software, But it would be possible if you have a Wishbone to to AXI bus bridge.. | 13:35 |
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| nickoe | _florent_: I tried it with latest litedram and it appears to have similar symptoms. I wonder why my sim is different to my hw. | 15:47 |
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| nickoe | zyp: Is it possible for the ClockDomainCrossing to overflow? | 16:37 |
| zyp | not if flow control is implemented | 16:38 |
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| nickoe | mmm!!! | 16:49 |
| nickoe | I think it is sort of an endianess problem | 16:49 |
| nickoe | I get 4x32 bits from the DMA thing, but I get the lowest address last. | 16:50 |
| nickoe | compare https://dpaste.com/E87NKBLM6 | 16:51 |
| tpb | Title: dpaste: E87NKBLM6 (at dpaste.com) | 16:51 |
| nickoe | https://i.snipboard.io/Dqf8TW.jpg | 16:51 |
| nickoe | Right there using the DMAReader from litevideo | 16:51 |
| nickoe | https://github.com/enjoy-digital/litevideo/blob/master/litevideo/output/core.py#L41-L122 | 16:54 |
| nickoe | https://github.com/nickoe/litex-boards/blob/f3090247db0a7d26291c39860eede3a3aa46ca64/litex_boards/targets/mars_ax3_custom.py#L133-L152 | 16:54 |
| nickoe | zyp: So that snippet of data dump is made with this code on the target https://dpaste.com/C7Y2HH8EZ.txt | 16:56 |
| nickoe | Why this difference on target and sim happens, I can't explain. | 17:01 |
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| nickoe | zyp: Someone in #symbiflow had the answer! :D This is happening because of the conversion from 128-bit native DRAM width to the 32-bit width requested here: https://github.com/nickoe/litex-boards/blob/f3090247db0a7d26291c39860eede3a3aa46ca64/litex_boards/targets/mars_ax3.py#L229 The solution is to add the parameter 'reverse=True' to the get port function call which will switch the order of 32-bit words when splitting a 128-bit word. | 21:49 |
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