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| _florent_ | nickoe: you use-case should be very similar to what is done in the VideoFramebuffer: LiteDRAMDMAReader (with native Data Width) --> 1) Clock Domain Crossing --> 2) Data Width Conversion to 32-bit. (1) and 2) order can be swapped depending on the Data Width and clock frequencies): https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/video.py#L605-L636 | 07:24 |
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| RaivisR | finally got one of the ddr3 chips cooperating on ecp5 vip, the trick was to force bank 7 vref to be used | 12:51 |
| RaivisR | also, using diamond to build and found that all pin constraints should be placed in single Misc(), otherwise Diamond takes the last one and resets all the other values to defaults for that last constraint | 12:52 |
| _florent_ | RaivisR: ah good | 13:13 |
| RaivisR | learning as I go, next step, both chips | 13:14 |
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| RaivisR | ok, now both chips work and with both toolchains, trellis and diamond | 14:16 |
| RaivisR | at sys_clk 50MHz | 14:18 |
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| zyp | _florent_, figured out the qspi problems I were having yesterday -- the flash chip on ecpix-5 (IS25LP256D) requires a «quad enable» bit to be set in the status register, otherwise it simply won't respond to the quad read command | 18:20 |
| zyp | I just tried the ulx3s as a sanity check, and that just worked | 18:22 |
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| zyp | reading a bit further up on it, it's non-volatile and most qspi flash chips appears to have the same, so it's just a matter of how it's been initialized | 18:48 |
| zyp | s/the same/the equivalent/ | 18:49 |
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| _florent_ | zyp: ah ok, I also remember spending some time on this on other boards, we should maybe add some comments in the core to check this | 19:34 |
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| nickoe | _florent_: hmm, cool. Using, self.comb += self.dma.source.connect(self.cdc.sink) does that also connect other signals like ready and valid up? | 20:04 |
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| zyp | nickoe, yes | 20:49 |
| nickoe | hmm | 20:50 |
| zyp | you can picture x.connect(y) as shorthand for y.data.eq(x.data), y.valid.eq(x.valid), x.ready.eq(y.ready) and so on | 20:50 |
| zyp | plus last/first | 20:51 |
| nickoe | I better try that, it should make it a lot simpler. | 20:51 |
| nickoe | But how do I control incrementing my address signal correctly then? | 20:51 |
| zyp | use connect when you're connecting endpoints to each other, use eq when you're manipulating the individual signals of an endpoint | 20:53 |
| zyp | you should probably have an address generator module with a source endpoint that outputs adresses | 20:54 |
| zyp | then you'll use eq inside the module to set the signals of the endpoint, and connect on the outside to connect this module to other modules | 20:54 |
| nickoe | I am not sure I understand the Endpoint()'s yet | 20:56 |
| zyp | an endpoint is essentially just a record for a stream | 20:57 |
| zyp | and a record is just a collection of signals | 20:57 |
| nickoe | Does the AsyncFIFO have an endpoint defined alread? | 20:58 |
| zyp | so a source endpoint is a collection of signals for a stream output from a module | 20:58 |
| zyp | yeah, AsyncFIFO has a sink and a source | 20:58 |
| leons | I'm currently working on some custom VexRiscv CPU configurations. I've noticed when starting from the "Secure" Vex variant and disabling caches (instruction and data) the bootloader will hang at "Booting from boot.json..." indefinitely | 21:00 |
| leons | Is this a known issue? Will try to reproduce on a clean LiteX head and standard board tomorrow | 21:01 |
| nickoe | zyp: ok, so I just added a proper clock domain https://github.com/nickoe/litex-boards/commit/407fcc426a1a9d00f760aef74bb23d235705c5c8 and then I should do the connect in here and maybe just have the address counter thing in the fsm of https://github.com/nickoe/litex-boards/blob/407fcc426a1a9d00f760aef74bb23d235705c5c8/litex_boards/targets/mars_ax3_custom.py#L66 ? | 21:03 |
| zyp | maybe, I like splitting stuff up into small self contained modules | 21:04 |
| nickoe | yeah, well, that is what I am -- mmm -- trying to | 21:10 |
| nickoe | zyp: What is the point of the ClockDomainCrossing object? | 21:15 |
| zyp | to cross clock domains? :) | 21:17 |
| nickoe | or does that use its own asyncfifo? | 21:17 |
| zyp | yes | 21:17 |
| nickoe | https://github.com/enjoy-digital/litex/blob/9bec0ce7a28afb498c7b7eb79943c270225c061a/litex/soc/interconnect/stream.py#L253 | 21:17 |
| zyp | IIRC a ClockDomainCrossing is a convenience wrapper around an AsyncFIFO | 21:18 |
| nickoe | ok, so I should just use the data from the self.cdc thing? | 21:18 |
| zyp | not sure what you mean | 21:18 |
| nickoe | I want to take my low rate data and push it to another downstram module | 21:19 |
| nickoe | the dac.v instance | 21:19 |
| zyp | so you've got a dac module in verilog? | 21:19 |
| nickoe | yes | 21:19 |
| zyp | have you already made a migen wrapper around it? | 21:19 |
| zyp | I'd put it into a migen wrapper with a sink endpoint | 21:20 |
| zyp | that way all you'll have to do from the outside is connect a suitable stream to the sink | 21:20 |
| nickoe | https://github.com/nickoe/litex-boards/blob/mars_ax3_sim/litex_boards/targets/mars_ax3_sim_litex.py#L329-L345 | 21:20 |
| zyp | yeah, not like that :) | 21:21 |
| nickoe | So I guess that is a "no" to the answer about a migen wrapper? | 21:21 |
| zyp | correct | 21:21 |
| zyp | you've instanced it directly in the SoC | 21:21 |
| zyp | see https://github.com/orbcode/orbtrace/blob/main/orbtrace/trace/__init__.py#L7 for an example of a wrapper around a verilog module | 21:22 |
| nickoe | mm, yeah, I think I just started from .. trying to get a verlog file included and it evolved from there. | 21:22 |
| zyp | this one got a source, not a sink, but is otherwise similar to what you want to do | 21:22 |
| nickoe | Ok, I will try | 21:23 |
| nickoe | I guess it should make it way easier to reuse in sim and implementation | 21:23 |
| zyp | yes | 21:23 |
| nickoe | Do I need to do "self.comb += ClockSignal().eq(traceclk)" for the DAC clock? | 21:27 |
| nickoe | or is that not needed, as all I need to do is wire up signals? | 21:27 |
| zyp | probably not | 21:27 |
| zyp | in my case the traceclk is an input that's driving the entire trace domain | 21:27 |
| nickoe | but it is clocked slower thann sys clk, but as I do no custom comb in the migen module I guess it does not matter+ | 21:30 |
| zyp | if you're gonna use the AsyncFIFO for cdc then migen needs to know about both domains | 21:31 |
| zyp | it can't do CDC without having both clocks available :) | 21:32 |
| nickoe | the add_source call to add the verilog file is a call on "platform", but how do I access that form within the module? | 21:35 |
| zyp | you'd need to pass it in | 21:36 |
| nickoe | ok | 21:36 |
| zyp | but you don't have to add it from the module itself | 21:36 |
| zyp | as long as it's added somewhere, it's fine | 21:36 |
| nickoe | mm, UnboundLocalError: local variable 'dac_vmodule' referenced before assignment, with https://dpaste.com/99WXY8G9P | 21:40 |
| tpb | Title: dpaste: 99WXY8G9P (at dpaste.com) | 21:40 |
| nickoe | and if I remove the + | 21:40 |
| nickoe | AttributeError: Attempted to assign special Module property - use += instead | 21:40 |
| nickoe | ... | 21:40 |
| zyp | the problem is line 13 | 21:40 |
| zyp | needs to be =, not += | 21:40 |
| nickoe | yes, and that is when I get above attribute error | 21:41 |
| zyp | nope | 21:41 |
| nickoe | https://dpaste.com/3GCQPPECT | 21:41 |
| tpb | Title: dpaste: 3GCQPPECT (at dpaste.com) | 21:41 |
| nickoe | :S | 21:41 |
| zyp | line 23 should still be += | 21:42 |
| zyp | ah | 21:42 |
| zyp | use self.submodules.dac = dac = … | 21:42 |
| nickoe | https://dpaste.com/CMYAYYXB7 | 21:42 |
| tpb | Title: dpaste: CMYAYYXB7 (at dpaste.com) | 21:42 |
| nickoe | oh | 21:43 |
| nickoe | I had self.submodules = dac = AlexandersDAC(platform, dac_plat, cd_dac) | 21:43 |
| zyp | yes | 21:43 |
| nickoe | sorry, my mistake, --- entirely.. of course. | 21:43 |
| nickoe | :) | 21:43 |
| nickoe | So now I have: | 21:47 |
| nickoe | https://github.com/nickoe/litex-boards/blob/mars_ax3_sim/litex_boards/targets/mars_ax3_sim_litex.py#L314-L317 | 21:47 |
| nickoe | and | 21:47 |
| nickoe | https://github.com/nickoe/litex-boards/blob/mars_ax3_sim/litex_boards/targets/mars_ax3_custom.py#L69-L125 | 21:47 |
| nickoe | zyp: ugh, so now it is connected correctly I think, https://i.snipboard.io/lTbhyc.jpg | 21:57 |
| nickoe | the dac_data_a should have been a nice sinusoid though..but that is probably the addressing going haywire | 21:57 |
| nickoe | I should somehow align the address increments with whatever is buffered | 22:01 |
| nickoe | What signal should I look for to attach it as an enable? | 22:01 |
| nickoe | zyp: mmm, getting closer, https://i.snipboard.io/1N32lK.jpg | 22:06 |
| nickoe | I added an If(cdc.sink.ready, NextValue(self.data_iq_addr, self.data_iq_addr + 1),), | 22:06 |
| nickoe | ^There are still some transients | 22:06 |
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