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| keesj | zyp: what is luna? | 07:38 |
|---|---|---|
| geertu | keesj: https://luna.readthedocs.io/en/latest/index.html | 07:44 |
| tpb | Title: LUNA: USB Multitool and Gateware Library LUNA documentation (at luna.readthedocs.io) | 07:44 |
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| shorne | somlo: FYI, on my board it seems I am reproducing the block transfer timeout even under the bios, hence sdcard booting is failing, adding printfs in the right place seems to fix it, but not a good solution: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/liblitesdcard/sdcard.c#L485-L490 (add printfs before each of these calls) | 08:15 |
| shorne | I am doing litescope tracing, and have a paper tracing the hole sdcard wiring to understand which wires best to probe, its taken me some time. | 08:17 |
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| keesj | wow... nice... I used the greatfet in my last security project with great effect but with the hardwork of putting this in migem some funky stuff will be possible | 09:17 |
| _florent_ | zyp: nice! | 10:31 |
| _florent_ | shorne: If you have a minimal repro on arty, I can also try to investigate on this. | 10:33 |
| zyp | tried hooking up a pair of ACM streams to the bios uart, and it's almost working: https://bin.jvnv.net/file/IGTkx.png :) | 10:33 |
| zyp | looking into where I'm dropping bytes now | 10:33 |
| _florent_ | zyp: How are you connecting it to the BIOS? Just with a UART module and connecting the sink/source streams to the ACM streams? | 10:35 |
| zyp | --uart-name stream, and then hooking up self.uart.sink and self.uart.source | 10:36 |
| tmbinc | zyp: very nice! | 10:40 |
| tmbinc | _florent_: on SDS1104X-E, is the ULPI accessible from PL, do you know? | 10:41 |
| tmbinc | or is that on MIO? | 10:41 |
| _florent_ | zyp: ok thanks, that's similar then. The behaviour could be a bit similar with self.user.source.ready not connected (and always 1), but I assume it is :) so that's probably something else... | 10:42 |
| _florent_ | self.user.source/self.uart.source | 10:43 |
| _florent_ | tmbinc: Sorry i don't know it but that would indeed be nice if accessible from the PL | 10:44 |
| tmbinc | It would also solve the situation on the SLA1016, which doesn't have ethernet (by default) | 10:44 |
| tmbinc | but to be fair, one could just add a UART on some pins somewhere... | 10:44 |
| tmbinc | it would also be interesting to have a wishbone-over-USB link :) | 10:45 |
| tmbinc | Can LUNA do that already? | 10:45 |
| _florent_ | tmbinc: BTW, sorry, I've been a bit busy with other things, I haven't yet been able to play with the ADC capture on the SDS1104X-E | 10:45 |
| tmbinc | yeah no worry, I'm busy as hell as well :) | 10:45 |
| tmbinc | This project sat idle for 3y+ before | 10:46 |
| tmbinc | It will survive a few more years | 10:46 |
| tmbinc | The SLA1016 though I'm really interested in getting alive because it would solve a real issue for me (namely that all my logic analyzers suck) | 10:46 |
| tmbinc | Whereas scope-wise I'm equipped relatively well (and to be fair, the Siglent firmware isn't _that_ bad) | 10:47 |
| _florent_ | For the SLA1016, while seeing you picture I was also wondering about ethernet | 10:47 |
| _florent_ | is it possible to add it easily? | 10:47 |
| tmbinc | I think so - I think it's "just" missing the PHY and passives | 10:48 |
| tmbinc | and the jack of course | 10:48 |
| tmbinc | I think it's 100MBit/s only again though | 10:48 |
| tmbinc | so maybe just making a USB breakout board/cable may not be a bad idea | 10:48 |
| tmbinc | Maybe even to USB host, and then ethernet | 10:48 |
| _florent_ | ok, with LiteICLink (https://github.com/enjoy-digital/liteiclink) it's possible to bridge wishbone in separate SoCs/Boards and it should probably be possible to run it over the SBUS connector | 10:50 |
| _florent_ | So connected to the SDS1104X it should probably be possible to just bridge the SDS1104X's wishbone bus to SLA1016's wishbone bus and just control the SLA1016 as we are controlling the SDS1104X | 10:51 |
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| tmbinc | Ah, not using USB then, but the differential IOs? | 10:56 |
| tmbinc | Did you see http://me.elitedvb.net/s/66ed5kBjgykrYFN ? (rough pinout description) | 10:57 |
| tpb | Title: Nextcloud (at me.elitedvb.net) | 10:57 |
| tmbinc | TL;DR it's ~6.8V power, USB, 3 diff pairs for which one is used for refclk (25MHz), trig in, and one unknown (likely trig out), as well as a few single ended IOs | 10:58 |
| tmbinc | The SBUS cable is 1:1 except for pin 4 and 7 swapped, so a regular HDMI cable won't work | 10:59 |
| tmbinc | (Plus a regular HDMI cable would not have the right pairs) | 10:59 |
| _florent_ | Thanks interesting, USB would probably be more interesting in standalone and LiteICLink when coupled with another board | 11:35 |
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| somlo | shorne: it makes sense that *timing* differences will trigger (or mask) the symptoms; it's just that when I tried to force the symptoms in the bios (by sprinkling extra delay loops into liblitesdcard/sdcard.c) I was unsuccessful; with Litex/Rocket I can only see it under Linux... | 14:50 |
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| zyp | I didn't realize the entirety of luna ran in the usb phy domain, adding cdc to the streams solved the problem: https://bin.jvnv.net/file/gw6KE.png :) | 19:41 |
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