| *** tpb has joined #litex | 00:00 | |
| *** rj has quit IRC | 00:17 | |
| *** rj has joined #litex | 00:21 | |
| *** lkcl_ has quit IRC | 00:24 | |
| *** lkcl_ has joined #litex | 00:37 | |
| shorne | _florent_: I have added some comments to the issue here | 00:44 |
|---|---|---|
| shorne | https://github.com/enjoy-digital/litesdcard/issues/22 | 00:44 |
| *** rj has quit IRC | 00:45 | |
| *** rozpruwacz has quit IRC | 00:51 | |
| *** lf_ has joined #litex | 00:51 | |
| *** lf has quit IRC | 00:51 | |
| *** shorne has quit IRC | 01:36 | |
| *** Bertl_oO is now known as Bertl_zZ | 01:50 | |
| *** pftbest has quit IRC | 02:05 | |
| *** shorne has joined #litex | 02:12 | |
| *** pftbest has joined #litex | 02:26 | |
| *** pftbest has quit IRC | 02:31 | |
| *** Degi_ has joined #litex | 02:56 | |
| *** Degi has quit IRC | 02:58 | |
| *** Degi_ is now known as Degi | 02:58 | |
| *** _whitelogger has quit IRC | 03:06 | |
| *** _whitelogger has joined #litex | 03:11 | |
| *** cr1901_modern has quit IRC | 06:02 | |
| *** kgugala_ has joined #litex | 06:20 | |
| *** kgugala has quit IRC | 06:23 | |
| *** rozpruwacz has joined #litex | 06:37 | |
| *** rozpruwacz has quit IRC | 06:42 | |
| *** cr1901_modern has joined #litex | 06:42 | |
| *** TMM has quit IRC | 06:44 | |
| *** TMM has joined #litex | 06:44 | |
| *** pftbest has joined #litex | 07:10 | |
| *** pftbest has quit IRC | 07:30 | |
| *** pftbest has joined #litex | 07:30 | |
| *** kgugala has joined #litex | 07:53 | |
| *** kgugala_ has quit IRC | 07:55 | |
| _florent_ | zyp: Great! | 08:20 |
| _florent_ | shorne: Thanks for looking at this. I'll try to reproduce and investigate too. If you don't mind, can you eventually add the bistream to the issue? This way I can first reproduce with your bitstream then try to build mine (I have the same setup with Arty + SDCard PMOD). | 08:22 |
| zyp | I'm gonna try making a withbone bridge compatible with the valentyusb one | 08:23 |
| *** Bertl_zZ is now known as Bertl | 08:46 | |
| _florent_ | Just for info, the BIOS size is now automatically reduced to the minimal size at the end of the build (with https://github.com/enjoy-digital/litex/commit/3cbdc567ff4c50610e3b67c8e7b4ece9fe4da628) | 08:52 |
| _florent_ | So playing with --integrated-rom-size when enabling/disabling features should not longer be required | 08:53 |
| zyp | nice | 08:53 |
| zyp | say, if I have a usb request handler in the usb clock domain that handles memory read and write requests, and I want to bring that over to the sys domain to attach it to the main interconnect, I figured I could map this to a request stream and a response stream | 09:20 |
| zyp | but since axilite is already based on streams, I guess I could use that rather than inventing my own | 09:21 |
| zyp | is there already a mechanism to handle cdc for axilite, or do I need to make my own class for that? | 09:24 |
| *** lkcl_ has quit IRC | 10:21 | |
| *** lkcl_ has joined #litex | 10:34 | |
| *** shorne has quit IRC | 10:38 | |
| *** lambda has quit IRC | 10:44 | |
| *** lambda has joined #litex | 11:00 | |
| *** lkcl_ has quit IRC | 12:42 | |
| *** Bertl is now known as Bertl_oO | 12:55 | |
| *** lkcl_ has joined #litex | 12:55 | |
| *** FFY00_ has quit IRC | 13:54 | |
| _florent_ | zyp: That would be nice/useful to add an AXILite CDC module, this would indeed consist of adding a CDC module on each stream | 14:01 |
| _florent_ | https://www.irccloud.com/pastebin/faTkYMwb/ | 14:02 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 14:02 |
| _florent_ | here is a skeleton completely untested in case you want to finish it and create a PR :) | 14:02 |
| zyp | yeah, that's what I had in mind, thanks | 14:03 |
| zyp | I'll test it once I get to that point, currently working on the usb request handles on the luna side | 14:04 |
| _florent_ | great, thanks | 14:05 |
| *** zoobab has joined #litex | 14:26 | |
| zoobab | does Litex support Zynq? I have a parallela board here taking dust | 14:27 |
| *** FFY00_ has joined #litex | 14:39 | |
| *** rj has joined #litex | 14:57 | |
| *** rj has quit IRC | 15:25 | |
| *** rj has joined #litex | 15:28 | |
| *** pftbest has quit IRC | 15:32 | |
| *** pftbest has joined #litex | 15:44 | |
| *** pftbest has quit IRC | 15:48 | |
| *** pftbest has joined #litex | 15:52 | |
| *** pftbest_ has joined #litex | 15:53 | |
| *** pftbest__ has joined #litex | 15:54 | |
| *** pftbest_ has quit IRC | 15:54 | |
| *** pftbest has quit IRC | 15:57 | |
| *** rj has quit IRC | 16:10 | |
| *** rj has joined #litex | 16:15 | |
| *** rj has quit IRC | 16:54 | |
| *** rj has joined #litex | 16:55 | |
| _florent_ | zoobab: Yes, you can create SoC on Zynq with or without the PS and interconnect the PL/PS through AXI, you can look at: | 17:23 |
| _florent_ | https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/zybo_z7.py | 17:24 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/zynq7000/core.py | 17:24 |
| _florent_ | This should give you an idea of what can be done. Basically you can just create regular LiteX SoCs and easily connect the PS to it | 17:25 |
| _florent_ | Connecting GP0 as a master for the LiteX SoC is done here for example: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/zybo_z7.py#L67-L73 | 17:26 |
| *** TMM has quit IRC | 17:33 | |
| *** TMM has joined #litex | 17:33 | |
| *** rj has quit IRC | 17:36 | |
| *** rj has joined #litex | 17:41 | |
| *** JH11 has joined #litex | 17:44 | |
| JH11 | Hi, I'm trying to run linux-on-vex-riscv project on my kc705 board but I'm running into lxterm issue towards the end of the project. When I'm trying to load the linux image over serial using lxterm --images=images/boot.json /dev/ttyUSB1 --speed=1e6. The bios prompt doesn't boot up or show any outputs... it just hangs there. Does anyone have a clue | 17:47 |
| JH11 | what might be the issue here? | 17:47 |
| *** JH11 has quit IRC | 17:50 | |
| *** JH11 has joined #litex | 17:50 | |
| *** rj has quit IRC | 18:19 | |
| gatecat | JH11: try --speed=500e3 for the kc705 | 18:19 |
| *** rj has joined #litex | 18:21 | |
| JH11 | I tried and it still gave me no outputs | 18:32 |
| JH11 | or bios prompt | 18:32 |
| JH11 | how long does it take to see the outputs usually? | 18:33 |
| gatecat | Should be pretty much straight away | 18:35 |
| gatecat | Do you see anything if you hit enter? | 18:36 |
| zoobab | on Alpine Linux, Litex does not find the xcompiler: | 19:00 |
| zoobab | OSError: Unable to find any of the cross compilation toolchains: | 19:00 |
| zoobab | - riscv64-unknown-elf | 19:00 |
| zoobab | - riscv64-unknown-linux-gnu | 19:00 |
| zoobab | - riscv32-unknown-elf | 19:00 |
| zoobab | while it is at: riscv-none-elf-gcc | 19:00 |
| zyp | you can try adding it to the list | 19:03 |
| zyp | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/__init__.py#L39 | 19:04 |
| zoobab | added | 19:04 |
| zoobab | works now | 19:04 |
| zoobab | will do a PR | 19:04 |
| *** rj has quit IRC | 19:05 | |
| *** rj has joined #litex | 19:08 | |
| zoobab | https://github.com/enjoy-digital/litex/pull/847 | 19:14 |
| JH11 | gatecat It doesnt show anything even if hit enter | 19:26 |
| JH11 | chmod -x bios.elf | 19:27 |
| JH11 | OBJCOPY bios.bin | 19:27 |
| JH11 | chmod -x bios.bin | 19:27 |
| JH11 | python3 -m litex.soc.software.mkmscimg bios.bin --little | 19:27 |
| JH11 | python3 -m litex.soc.software.memusage bios.elf /home/jhu96/Desktop/McGill_Masters/Research/linux-on-litex-vexriscv/build/kc705/software/bios/../include/generated/regions.ld riscv64-unknown-elf | 19:27 |
| JH11 | ROM usage: 47.38KiB (74.02%) | 19:27 |
| JH11 | RAM usage: 0.77KiB (9.57%) | 19:27 |
| JH11 | make: Leaving directory '/home/jhu96/Desktop/McGill_Masters/Research/linux-on-litex-vexriscv/build/kc705/software/bios' | 19:27 |
| JH11 | Open On-Chip Debugger 0.11.0+dev-00034-g4c00f96fc-dirty (2021-03-11-15:25) | 19:27 |
| JH11 | Licensed under GNU GPL v2 | 19:27 |
| JH11 | For bug reports, read | 19:27 |
| JH11 | http://openocd.org/doc/doxygen/bugs.html | 19:27 |
| JH11 | DEPRECATED! use 'adapter driver' not 'interface' | 19:27 |
| JH11 | Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. | 19:27 |
| tpb | Title: OpenOCD: Bug Reporting (at openocd.org) | 19:27 |
| JH11 | DEPRECATED! use 'adapter speed' not 'adapter_khz' | 19:27 |
| JH11 | fpga_program | 19:27 |
| JH11 | Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling" | 19:27 |
| JH11 | Info : clock speed 25000 kHz | 19:27 |
| JH11 | gatecat this is the last bit of my uploading the bitstream onto the kc705 board. Was I able to upload it correctly? | 19:28 |
| JH11 | gatecat i think it looked fine to me | 19:28 |
| *** FFY00_ has quit IRC | 19:47 | |
| *** rj has quit IRC | 19:48 | |
| *** FFY00_ has joined #litex | 19:49 | |
| *** rj has joined #litex | 19:52 | |
| JH11 | Does anyone have a clue why lxterm --images=images/boot.json /dev/ttyUSB2 --speed=500e3 is stuck for loading linux to kc705 board with Jtag/Serial? | 20:10 |
| JH11 | even if i press enter after that command | 20:11 |
| zyp | _florent_, the axi-lite cdc seems to work fine, had to s/layout/description/, but otherwise it appears fully functional (at least the read side) | 20:20 |
| zyp | I've only finished the read handler so far, but here's writing the scratch register via the bios shell and reading it back over the usb bridge: https://bin.jvnv.net/file/JABjY.png | 20:21 |
| *** rj has quit IRC | 20:32 | |
| *** rj has joined #litex | 20:35 | |
| geertu | Finally I got v5.12-rc2 booting on vexriscv. Patch sent upstream. | 20:43 |
| _florent_ | zyp: nice, thanks for the feedback, I'll integrate it in interconnect.axi soon then | 20:51 |
| _florent_ | geertu: great, thanks for looking at this (and your previous help on 5.11) | 20:56 |
| *** pftbest__ has quit IRC | 21:01 | |
| *** pftbest has joined #litex | 21:01 | |
| *** rj has quit IRC | 21:15 | |
| *** rj has joined #litex | 21:18 | |
| *** shorne has joined #litex | 21:19 | |
| *** pftbest has quit IRC | 21:25 | |
| *** pftbest has joined #litex | 21:26 | |
| *** pftbest has quit IRC | 21:30 | |
| *** pftbest has joined #litex | 21:30 | |
| *** rj has quit IRC | 21:31 | |
| *** rj has joined #litex | 21:31 | |
| *** pftbest has quit IRC | 21:33 | |
| *** pftbest has joined #litex | 21:51 | |
| *** pftbest has quit IRC | 21:55 | |
| *** rj has quit IRC | 22:01 | |
| *** rj has joined #litex | 22:05 | |
| *** kgugala has quit IRC | 22:15 | |
| *** kgugala has joined #litex | 22:16 | |
| shorne | _florent_: attached | 22:27 |
| *** rj has quit IRC | 22:44 | |
| *** rj has joined #litex | 22:48 | |
| zyp | https://paste.jvnv.net/view/nyEvK | 22:49 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 22:49 |
| zyp | I ran a rough comparison vs etherbone, it's a little bit slower -- 26.6 seconds to transfer a big litescope buffer over usb vs 19.7 seconds over etherbone | 23:00 |
| *** shorne has quit IRC | 23:00 | |
| *** rj has quit IRC | 23:27 | |
| *** rj has joined #litex | 23:31 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!
