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| shorne | interesting, I have been having issues with litex bios booting linux off sdcard, when I turn on sdcard_debug it boots, when I turn if off it doesnt boot | 04:54 |
|---|---|---|
| shorne | it looks like some kind of timing issue | 04:54 |
| shorne | with some debug it shows the f_mount call fails | 05:37 |
| shorne | looking more | 05:37 |
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| shorne | Is there a fast way to flash a new bios to the board? If I make c changes and do " ./arty.py ..platform options.. --load " it doesn't update the bios | 06:42 |
| shorne | I seem to have to do "./arty.py ...option... --build; ./arty.py ...options... --load" which requires waiting for the bitstream to build | 06:43 |
| shorne | the --no-compile-gateware option doesn't seem to do anything | 06:44 |
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| zyp | the bios is stored in blockram initialization in the bitstream so updating it requires either rebuilding the bitstream or rewriting the bitstream to change blockram contents, and I don't think the latter is supported | 06:56 |
| shorne | zyp: thats what I figured, but wasn't sure, thanks for clarifying | 07:04 |
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| _florent_ | shorne: That's not supported directly in the LiteX-Targets, but it's possible to easily rebuild the BIOS and reload it | 07:55 |
| _florent_ | With a bridge in your SoC (for example JTAGBone in your case), you can set integrated_rom_mode to "rw": https://github.com/enjoy-digital/litedram/blob/master/bench/arty.py#L76 | 07:56 |
| _florent_ | and then use a simple script to reload the ROM and reset the SoC: https://github.com/enjoy-digital/litedram/blob/master/bench/common.py#L95-L109 | 07:57 |
| _florent_ | in case reseting the full SoC breaks the bridge, you could comment this: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L939-L944 | 07:59 |
| _florent_ | this will only reset the CPU and not the whole SoC | 07:59 |
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| _florent_ | nats`: Thanks for the minimal repro, this was an issue in LiteX, the default CRG is probably not used that often: https://github.com/enjoy-digital/litex/commit/e48b269d77567e251d34bd501d8cb390a91ee675 | 09:54 |
| _florent_ | nats`: I'm planning to cleanup/improve litex.build in not too long... | 09:59 |
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| shorne | _florent_: thanks, I will try that tomorrow | 11:41 |
| shorne | the sdcard failing to boot seems mostly due to something wrong with how I built my sdcard partition table/fat32 filesystem | 11:42 |
| shorne | I am not sure why enabling sdcard_debug statements fixes the issue, but I am trying to get to the root cause | 11:43 |
| gatecat | anyone seen "TypeError: Expression of unrecognized type: 'ClockSignal'" before? | 12:04 |
| gatecat | it seems to be related to using `wishbone.SRAM` to read from a memory | 12:05 |
| gatecat | ah, my error, wishbone.SRAM isn't supposed to be a submodule | 12:10 |
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| somlo | shorne: with libfatfs all FAT partition sizes *should* work, but empirically I've had better luck with fat16 | 12:29 |
| somlo | * in LiteX bios (i.e., for booting from the sdcard) | 12:31 |
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| nats` | _florent_, you mean that using the default clock isn't mapped correctly ? | 12:47 |
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| _florent_ | nats`: There was a typo in the code preventing the constraint to be generated. | 18:02 |
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| shorne | _florent_: it does seem to work, after the rom load and reset I need to wait about 30 seconds (maybe jtag transfer?) | 19:49 |
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| zyp | in case anyone is interested; I started building a wrapper around luna: https://paste.jvnv.net/view/ODFvB | 22:32 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 22:32 |
| zyp | just had my first luna-in-litex USBDevice enumerate :) haven't tested the streams yet | 22:33 |
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